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programmable controller for capacitance touch sensors AD7143 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007 analog devices, inc. all rights reserved. features programmable capacitance-to-digital converter 25 ms update rate (@ maximum sequence length) better than 1 ff resolution 8 capacitance sensor input channels no external rc tuning components required automatic conversion sequencer on-chip automatic calibration logic automatic compensation for environmental changes automatic adaptive threshold and sensitivity levels on-chip ram to store calibration data i 2 c?-compatible serial interface separate vdrive level for serial interface interrupt output for host controller 16-lead, 4 mm x 4 mm lfcsp-vq 2.6 v to 3.6 v supply voltage low operating current full power mode: less than 1 ma low power mode: 50 a applications personal music and multimedia players cell phones digital still cameras smart hand-held devices television, a/v, and remote controls gaming consoles functional block diagram cshield src gnd cin0 cin1 cin2 cin3 cin4 cin5 cin6 cin7 vdrive vcc 16-bit - cdc switch matrix 15 16 1 2 3 4 5 6 9 10 7 8 250khz excitation source control and data registers calibra- tion engine calibra- tion ram power-on reset logic sda sclk int interrupt logic i 2 c serial interface and control logic 13 14 12 11 AD7143 06472-001 figure 1. general description the AD7143 is an integrated capacitance-to-digital converter (cdc) with on-chip environmental calibration for use in systems requiring a novel user input method. the AD7143 interfaces to external capacitance sensors implementing functions, such as capacitive buttons, scroll bars, and scroll wheels. the cdc has eight inputs channeled through a switch matrix to a 16-bit, 250 khz sigma-delta (-) capacitance-to-digital converter. the cdc is capable of sensing changes in the capacitance of the external sensors and uses this information to register a sensor activation. the external sensors can be arranged as a series of buttons, as a scroll bar or wheel, or as a combination of sensor types. by programming the registers, the user has full control over the cdc setup. high resolution sensors require software to run on the host processor. the AD7143 has on-chip calibration logic to account for changes in the ambient environment. the calibration sequence is performed automatically and at continuous intervals, while the sensors are not touched. this ensures that there are no false or nonregistering touches on the external sensors due to a changing environment. the AD7143 has an i 2 c-compatible serial interface and a separate vdrive pin for i 2 c serial interface operating voltages between 1.65 v and 3.6 v. the AD7143 is available in a 16-lead, 4 mm 4 mm lfcsp-vq and operates from a 2.6 v to 3.6 v supply. the operating current consumption is less than 1 ma, falling to 50 a in low power mode (conversion interval of 400 ms).
AD7143 rev. 0 | page 2 of 56 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 i 2 c timing specifications ............................................................ 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configurations and function descriptions ........................... 7 typical performance characteristics ............................................. 8 theory of operation ...................................................................... 11 capacitance sensing theory ..................................................... 11 operating modes ........................................................................ 12 capacitance sensor input configuration .................................... 13 cin input multiplexer setup .................................................... 13 capacitiance-to-digital converter ............................................... 14 oversampling the cdc output ............................................... 14 capacitance sensor offset control .......................................... 14 conversion sequencer ............................................................... 14 cdc conversion sequence time ............................................ 15 cdc conversion results ........................................................... 16 noncontact proximity detection ................................................. 17 recalibration ............................................................................... 17 proximity sensitivity .................................................................. 17 slow fifo .................................................................................... 19 slow_filter_update_lvl .............................................. 19 environmental calibration ........................................................... 22 capacitance sensor behavior without calibration ................ 22 capacitance sensor behavior with calibration ...................... 23 adaptive threshold and sensitivity ............................................. 25 interrupt output ............................................................................. 26 cdc conversion complete interrupt ..................................... 26 sensor touch interrupt .............................................................. 26 serial interface ................................................................................ 28 i 2 c compatible interface ........................................................... 28 pcb design guidelines ................................................................. 31 capacitive sensor board mechanical specifications ............. 31 chip scale packages ................................................................... 31 power-up sequence ....................................................................... 32 typical application circuits ......................................................... 33 register map ................................................................................... 34 detailed register descriptions ..................................................... 35 bank 1 registers ......................................................................... 35 bank 2 registers ......................................................................... 43 bank 3 registers ......................................................................... 47 outline dimensions ....................................................................... 55 ordering guide .......................................................................... 55 revision history 1/07revision 0: initial version
AD7143 rev. 0 | page 3 of 56 specifications v cc = 2.6 v to 3.6 v, t a = ?40 o c to +85c, unless otherwise noted. table 1. parameter min typ max unit test conditions/comments capacitance-to-digital converter update rate 23 25 26 ms eight conversion stages in sequencer, decimation = 256 resolution 16 bit cin input range 1 2 pf no missing codes 16 bit guaranteed by design, but not production tested cin input leakage 25 na total unadjusted error 20 % output noise (peak-to-peak) 7 codes decimation rate = 128 3 codes decimation rate = 256 output noise (rms) 0.8 codes decimation rate = 128 0.5 codes decimation rate = 256 parasitic capacitance 40 pf parasitic capacitance to ground, per cin input guaranteed by characterization c bulk offset range 1 20 pf c bulk offset resolution 156.25 ff low power mode delay accuracy 5 % % of 200 ms, 400 ms, 600 ms, or 800 ms excitation source frequency 237.5 240 262.5 khz output voltage vcc v short-circuit source current 20 ma short-circuit sink current 50 ma maximum output load 250 pf capacitance load on source to ground c shield output drive 10 a c shield bias level vcc/2 v logic inputs (sclk, sda) v ih input high voltage 0.7 v drive v v il input low voltage 0.4 v i ih input high voltage ?1 a i il input low voltage 1 a v in = gnd hysteresis 150 mv open-drain output s (sclk, sda, int ) v ol output low voltage 0.4 v i sink = ?1 ma i oh output high leakage current +0.1 1 a power v cc 2.6 3.3 3.6 v v drive 1.65 3.6 v i cc 0.9 1 ma in full power mode 20 a low power mode, converter idle, t a = 25c 16 30 a low power mode, converter idle 4.5 a full shutdown, t a = 25c 2.25 15 a full shutdown 1 c in and c bulk are defined as follows: plastic overlay sensor board c bulk c in capacitive sensor 05702-054
AD7143 rev. 0 | page 4 of 56 table 2. typical average current in low power mode, v cc = 3.6 v, t = 25c, load of 50 pf on src pin number of conversion stages, current values expressed in a low power mode delay decimation rate 1 2 3 4 5 6 7 8 200 ms 128 26.4 33.3 40.1 46.9 53.5 60 66.5 72.8 256 35.6 49.1 62.2 74.9 87.3 99.3 111 122.3 400 ms 128 21.3 24.8 28.3 31.7 35.2 38.6 42 45.4 256 26 32.9 39.7 46.5 53.1 59.6 66.1 72.4 600 ms 128 19.6 21.9 24.3 26.6 28.9 31.2 33.5 35.8 256 22.7 27.4 32 25.6 41.1 45.6 50 54.4 800 ms 128 18.7 20.5 22.2 24 25.7 27.5 29.2 31 256 21.1 24.6 28.1 31.5 35 38.4 41.8 45.2 table 3. maximum average current in low power mode, v cc = 3.6 v, load of 50 pf on src pin number of conversion stages, current values expressed in a low power mode delay decimation rate 1 2 3 4 5 6 7 8 200 ms 128 42.2 50.5 58.7 66.7 74.6 82.3 90.0 97.5 256 53.2 69.3 84.9 100.0 114.6 128.7 142.5 155.8 400 ms 128 36.1 40.4 44.5 48.7 52.8 56.9 60.9 64.5 256 41.8 50.1 58.2 66.2 74.1 82.0 89.5 97.1 600 ms 128 34.1 37.0 39.7 42.5 45.3 48.1 50.8 53.4 256 37.9 43.5 49.0 54.5 60.0 65.2 70.5 75.7 800 ms 128 33.1 35.2 37.3 39.4 41.5 43.6 45.7 47.7 256 35.9 40.1 44.3 48.4 52.6 56.6 60.7 64.7
AD7143 rev. 0 | page 5 of 56 i 2 c timing specifications t a = ?40c to +85c, v cc = 2.6 v to 3.6 v, unless otherwise noted. sample tested at 25c to ensure compliance. all input signals timed from a voltage level of 1.6 v. table 4. i 2 c timing specifications 1 parameter limit unit description f sclk 400 khz max t 1 0.6 s min start condition hold time, t hd; sta t 2 1.3 s min clock low period, t low t 3 0.6 s min clock high period, t high t 4 100 ns min data setup time, t su; dat t 5 300 ns min data hold time, t hd; dat t 6 0.6 s min stop condition setup time, t su; sto t 7 0.6 s min start condition setup time, t su; sta t 8 1.3 s min bus free time between stop and start conditions, t buf t r 300 ns max clock/data rise time t f 300 ns max clock/data fall time 1 guaranteed by design, not production tested. 200a i ol 200a i oh 1.6v to output pin c l 50pf 06472-003 figure 2. load circuit for digita l output timing specifications
AD7143 rev. 0 | page 6 of 56 absolute maximum ratings parameter rating vcc to gnd ?0.3 v to +3.6 v analog input voltage to gnd ?0.3 v to vcc + 0.3 v digital input voltage to gnd ?0.3 v to vdrive + 0.3 v digital output voltage to gnd ?0.3 v to vdrive + 0.3 v input current to any pin except supplies 1 10 ma esd rating (human body model) 2.5 kv operating temperature range ?40c to +150c storage temperature range ?65c to +150c junction temperature 150c lfcsp_vq power dissipation 450 mw ja thermal impedance 135.7c/w ir reflow peak temperature 260c (0.5c) lead temperature (soldering 10 sec) 300c 1 transient currents of up to 100 ma do not cause scr latch-up. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
AD7143 rev. 0 | page 7 of 56 pin configurations and function descriptions pin 1 indicator 1 cin2 2 cin3 3 cin4 4 cin5 11 vdrive 12 sda 10 gnd 9vcc 5 c i n 6 6 c i n 7 7 c s h i e l d 8 s r c 1 5 c i n 0 1 6 c i n 1 1 4 i n t 1 3 s c l k AD7143 top view (not to scale) 06472-004 figure 3. pin configuration table 5. pin function descriptions pin no. mnemonic description 1 cin2 capacitance sensor input. 2 cin3 capacitance sensor input. 3 cin4 capacitance sensor input. 4 cin5 capacitance sensor input. 5 cin6 capacitance sensor input. 6 cin7 capacitance sensor input. 7 cshield cdc shield potential output. requires 10 nf capacitor to ground. 8 src cdc excitation source output. 9 vcc cdc supply voltage. 10 gnd ground reference point for all cdc circuitry. tie to ground plane. 11 vdrive i 2 c serial interface operating voltage 12 sda i 2 c serial data input/output. sd a requires pull-up resistor. 13 sclk clock input for serial interface. sclk requires pull-up resistor. 14 int general-purpose open-drain interrupt output. programmable polarity; requires pull-up resistor. 15 cin0 capacitance sensor input. 16 cin1 capacitance sensor input.
AD7143 rev. 0 | page 8 of 56 typical performance characteristics i cc (a) v cc (v) 820 860 840 920 900 880 940 960 980 1000 2.7 2.92.8 3.0 3.1 3.2 3.3 3.4 3.5 3.6 device 3 device 1 device 2 06472-005 figure 4. supply current vs. supply voltage 2.72.82.93.03.13.2 3.4 3.3 3.5 3.6 i cc (a) v cc (v) 40 60 100 80 120 140 160 180 lp_conv_delay = 200ms lp_conv_delay = 400ms lp_conv_delay = 600ms lp_conv_delay = 800ms 06472-006 figure 5. low power supply current vs. supply voltage, decimation rate = 256 2.7 2.8 2.9 3.0 3.1 3.2 3.43.3 3.5 3.6 i cc (a) v cc (v) 20 40 60 80 100 120 lp_conv_delay = 200ms lp_conv_delay = 600ms lp_conv_delay = 800ms lp_conv_delay = 400ms 06472-007 figure 6. low power supply current vs. supply voltage decimation rate = 128 1.40 1.55 1.70 1.85 2.00 2.15 2.30 2.45 2.7 2.9 2.8 3.03.13.23.33.43.53.6 shutdown i cc (a) v cc (v) device 2 device 3 device 1 06472-008 figure 7. shutdown supply current vs. supply voltage 1.10 1.05 1.00 0.95 0.90 0.85 0.80 0 50 100 150 200 250 300 350 400 450 500 i cc (ma) capacitance load on source (pf) device 3 device 2 device 1 06472-009 figure 8. supply current vs. capacitive load on src 16015 16010 16005 16000 15995 15990 15985 15980 0 50 100 150 200 250 300 350 400 450 500 cdc output code capacitance load on source (pf) device 3 device 2 device 1 06472-010 figure 9. output code vs. capacitive load on src
AD7143 rev. 0 | page 9 of 56 960 780 800 820 840 860 880 900 920 940 ?40 120 100 3.6v 3.3v 2.7v 80604020 0 ?20 supply current (a) temperature (c) 06472-011 figure 10. supply current vs. temperature 12 10 8 6 4 2 0 ?40 120 100 806040 2.7v 3.3v 20 0 ?20 supply current (a) temperature (c) 3.6v 06472-012 figure 11. shutdown suppl y current vs. temperature 4.8 1.3 0 10k 20k 30k 40k 50k 60k 06472-045 cdc output code capacitance (pf) 4.3 3.8 3.3 2.8 2.3 1.8 cdc output code figure 12. 3.3 v linearity 06472-046 0.020 ?0.010 error (pf) 0.015 0.010 0.005 0 ?0.005 0 70k cdc output code 10k 20k 30k 40k 50k 60k cdc output code figure 13. 3.3 v linearity error 2.5 2.0 1.5 1.0 0.5 0 10 10m 100k 1k cdc peak-to-peak noise (codes) frequency (hz) 100mv 200mv 300mv 400mv 500mv 06472-013 figure 14. power supply sine wave rejection 180 160 140 120 100 80 60 40 20 0 100 10m 25mv 100mv 200mv 300mv 1m 10k 100k 1k cdc peak-to-peak noise (codes) square wave frequency (hz) 50mv 06472-014 figure 15. power supply square wave rejection
AD7143 rev. 0 | page 10 of 56 0 32900 31900 06 06472-047 pcb parasitic capacitance (pf) cdc output code (d) 32800 32700 32600 32500 32400 32300 32200 32100 32000 10 20 30 40 50 parasitic capacitance figure 16. cdc output code s vs. parasitic capacitance
AD7143 rev. 0 | page 11 of 56 theory of operation the AD7143 is a capacitance-to-digital converter (cdc) with on-chip environmental compensation, intended for use in portable systems requiring high resolution user input. the internal circuitry consists of a 16-bit, - converter that converts a capacitive input signal into a digital value. there are eight input pins, cin0 to cin7, on the AD7143. a switch matrix routes the input signals to the cdc. the result of each capacitance-to-digital conversion is stored in on-chip registers. the host subsequently reads the results over the serial interface. the AD7143 has an i 2 c interface, ensuring that the parts are compatible with a wide range of host processors. the AD7143 interfaces with up to eight external capacitance sensors. these sensors can be arranged as buttons, scroll bars, wheels, or as a combination of sensor types. the external sensors consist of electrodes on a single or multiple layer pcb that interface directly to the AD7143. the AD7143 can be set up to implement any set of input sensors by programming the on-chip registers. the registers can also be programmed to control features such as averaging, offsets, and gains for each of the external sensors. there is a sequencer on-chip to control how each of the capacitance inputs is polled. the AD7143 has on-chip digital logic and 528 words of ram used for environmental compensation. the effects of humidity, temperature, and other environmental factors can effect the operation of capacitance sensors. transparent to the user, the AD7143 performs continuous calibration to compensate for these effects, allowing the AD7143 to give error-free results at all times. the AD7143 requires some minor companion software that runs on the host or other microcontroller to implement high resolution sensor functions, such as a scroll bar or wheel. however, no host software is required to implement buttons, including 8-way button functionality. button sensors are implemented completely in digital logic on-chip with the status of each button reported in interrupt status registers. the AD7143 can be programmed to operate in either full power mode, or in low power automatic wake-up mode. the automatic wake-up mode is particularly suited for portable devices that require low power operation giving the user significant power savings coupled with full functionality. the AD7143 has an interrupt output, int , to indicate when new data has been placed into the registers. int is used to interrupt the host on sensor activation. the AD7143 operates from a 2.6 v to 3.6 v supply, and is available in a 16-lead, 4 mm 4 mm lfcsp_vq. capacitance sensing theory the AD7143 uses a method of sensing capacitance known as the shunt method. using this method, an excitation source is connected to a transmitter generating an electric field to a receiver. the field lines measured at the receiver are translated into the digital domain by a - converter. when a finger, or other grounded object, interferes with the electric field, some of the field lines are shunted to ground and do not reach the receiver (see figure 17 ). therefore, the total capacitance measured at the receiver decreases when an object comes close to the induced field. excitation signal 250khz - adc 16-bit data plastic cove r AD7143 tx rx pcb layer 06472-015 figure 17. single layer sensing capacitance method in practice, the excitation source and - adc are implemented on the AD7143, while the transmitter and receiver are constructed on a pcb that comprises the external sensor. registering a sensor activation when a sensor is approached, the total capacitance associated with that sensor, measured by the AD7143, changes. when the capacitance changes to such an extent that a set threshold is exceeded, the AD7143 registers this as a sensor touch and then automatically updates the internal interrupt status registers. preprogrammed threshold levels are used to determine if a change in capacitance is due to a button being activated. if the capacitance exceeds one of the threshold limits, the AD7143 registers this as a true button activation. the same threshold principle is used to determine if other types of sensors, such as sliders or scroll wheels, are activated.
AD7143 rev. 0 | page 12 of 56 complete solution for capacitance sensing analog devices, inc. provides a complete solution for capacitance sensing. the two main elements to the solution are the sensor pcb and the AD7143. if the application requires high resolution sensors, such as scroll bars or wheels, software is required that runs on the host processor. (no software is required for button sensors.) the memory requirements for the host depend upon the sensor, and are typically 9 kb of code and 600 bytes of data memory. AD7143 sensor pcb s1 s2 s3 s7 s6 s5 s4 s8 src 8 i 2 c host processor 1 mips 9kb rom 600 bytes ram 06472-016 figure 18. three part capacitance sensing solution analog devices supplies the sensor pcb footprint design libraries to the customer based on the customers specifications, and supplies any necessary software on an open-source basis. operating modes the AD7143 has three operating modes. full power mode, where the device is always fully powered, is suited for applications where power is not a concern. one example is game consoles that have an ac power supply. low power mode, where the part automatically powers down, is tailored to give significant power savings over full power mode, and is suited for mobile applications where power must be conserved. in shutdown mode, the part shuts down completely. the power_mode bits (bit 0 and bit 1) of the control register set the operating mode on the AD7143. the control register is at address 0x000. table 6 shows the power_mode settings for each operating mode. to put the AD7143 into shutdown mode, set the power_mode bits to either 01 or 11. table 6. power_mode settings power_mode bits operating mode 00 full power mode 01 full shutdown mode 10 low power mode 11 full shutdown mode the power-on default setting of the power_mode bits is 00, full power mode. full power mode in full power mode, all sections of the AD7143 remain fully powered at all times. while a sensor is being touched, the AD7143 processes the sensor data. if no sensor is touched, the AD7143 measures the ambient capacitance level and uses this data for the on-chip compensation routines. in full power mode, the AD7143 converts at a constant rate. see the cdc conversion sequence time section for more information. low power mode when in low power mode, the AD7143 power_mode bits are set to 10 upon device initialization. if the external sensors are not touched, the AD7143 reduces its conversion frequency, thereby greatly reducing its power consumption. the part remains in a reduced power state when the sensors are not touched. every lp_conv_delay ms (200 ms, 400 ms, 600 ms or 800 ms), the AD7143 performs a conversion and uses this data to update the compensation logic. when an external sensor is touched, the AD7143 begins a conversion sequence every 25 ms to read back data from the sensors. in low power mode, the total current consumption of the AD7143 is an average of the current used during a conversion, and the current used while the AD7143 is waiting for the next conversion to begin. for example, when lp_conv_delay is 400 ms, the AD7143 typically uses 0.9 ma current for 25 ms and 15 a for 400 ms of the conversion interval. note that these conversion timings can be altered through the register settings. see the cdc conversion sequence time section for more information. no yes yes no timeout AD7143 setup and initialization power_mode = 10 any sensor touched? conversion sequence every lp_conv_delay ms update compensation logic data path proximity timer count down conversion sequence every 25ms for sensor readback any sensor touched? 06472-017 figure 19. low power mode operation the time taken for the AD7143 to go from a full power state to a reduced power state, once the user stops touching the external sensors, is configurable. once the sensors are not touched, the pwr_dwn_timeout bits, in the ambient compensation ctrl 0 register at address 0x002, control the amount of time necessary for the device to return to a reduced power state.
AD7143 rev. 0 | page 13 of 56 capacitance sensor input configuration each input connection from the external capacitance sensors to the AD7143 converter can be uniquely configured by using the registers in table 38 and tabl e 3 9 . these registers are used to configure input pin connection setups, sensor offsets, sensor sensitivities, and sensor limits for each stage. each sensor can be individually optimized. for example, a button sensor connected to stage0 can have a different sensitivity and offset values than a button with a different function that is connected to a different stage. cin input multiplexer setup the cin_connection_setup registers in table 38 list the available options for connecting the sensor input pin to the cdc. the AD7143 has an on-chip multiplexer to route the input signals from each pin to the input of the converter. each input pin can be tied to either the negative or the positive input of the cdc or can be left floating. each input can also be internally connected to the c shield signal to help prevent cross coupling. if an input is not used, always connect it to c shield . connecting a cinx input pin to the positive cdc input results in a decrease in cdc output code when the corresponding sensor is activated. connecting a cinx input pin to the negative cdc input results in an increase in cdc output code when the corresponding sensor is activated. two bits in each sequencer stage register control the mux setting for the input pin. cin connection setup bits cin setting 00 cinx floating 01 cinx connected to negative cdc input 10 cinx connected to positive cdc input 11 cinx connected to internal bias cin0 cin1 cin2 cin3 cin4 cin5 cin6 cin7 + ? cdc 06472-018 figure 20. input mux configuration options
AD7143 rev. 0 | page 14 of 56 capacitiance-to-digital converter the capacitance-to-digital converter on the AD7143 has a - architecture with 16-bit resolution. eight possible inputs to the cdc are connected to the input of the converter through a switch matrix. the sampling frequency of the cdc is 250 khz. oversampling the cdc output the decimation rate, or oversampling ratio, is determined by bits[9:8] of the pwr_control register located at address 0x000 and listed in table 7 . table 7. cdc decimation rate decimation bit value decimation rate cdc output rate per stage 00 256 3.072 ms 01 128 1.525 ms 10 1 C C 11 1 C C 1 do not use this setting. the decimation process on the AD7143 is an averaging process where a number of samples are taken and the averaged result is output. due to the architecture of the digital filter employed, the amount of samples taken (per stage) is equal to 3 the decimation rate. therefore, 3 256 or 3 128 samples are averaged to obtain each stage result. the decimation process reduces the amount of noise present in the final cdc result. however, the higher the decimation rate, the lower the output rate per stage thus, a trade-off is possible between a noise free signal and speed of sampling. capacitance sensor offset control there are two programmable dacs on board the AD7143 to null any capacitance sensor offsets. these offsets are associated with printed circuit board capacitance or capacitance due to any other source, such as connectors. in figure 21 , c in is the capacitance of the input sensors, while c bulk is the capacitance between layers of the sensor pcb. c bulk can be offset using the on-board dacs. plastic overlay sensor board c bulk c in capacitive sensor 0 6472-019 figure 21. capacitances around the sensor pcb a simplified block diagram in figure 22 shows how to apply the stage_offset registers to null the offsets. the 7-bit pos_afe_offset and neg_afe_offset registers program the offset dac to provide 0.16 pf resolution offset adjustment over a range of 20 pf. apply the positive and negative offsets to either the positive or the negative cdc input using the neg_afe_offset register and pos_afe_offset register. this process is only required once during the initial capacitance sensor characterization. pos_afe_offset 16-bit cdc neg_afe_offset +dac (20pf range) 7 7 16 cin src cin_connection_setup register senso r ?dac (20pf range) + _ 0 6472-020 pos_afe_offset_swap bit neg_afe_offset_swap bit figure 22. analog front-end o ffset control conversion sequencer the AD7143 has an on-chip sequencer to implement conversion control for the input channels. up to eight conversion stages can be performed in sequence. each of the eight conversion stages can measure an input from a different sensor. by using the bank 2 registers, each stage can be uniquely configured to support multiple capacitance sensor interface requirements. for example, a sensor s1 can be assigned to stage1 and sensor s2 assigned to stage2. the AD7143 on-chip sequence controller provides conversion control beginning with stage0. figure 23 shows a block diagram of the cdc conversion stages and cin inputs. a conversion sequence is a sequence of cdc conversions starting at stage0 and ending at the stage determined by the value programmed in the sequence_stage_num register. depending on the number and type of capacitance sensors used, not all conversion stages are required. use the sequence_stage_num register to set the number of conversions in one sequence, depending on the sensor interface requirements. for example, this register is set to 5 if the cin inputs are mapped to only six stages. in addition, set the stage_cal_en registers according to the number of stages that are used.
AD7143 rev. 0 | page 15 of 56 stage7 stage6 stage5 stage4 stage3 stage2 stage1 stage0 switch matrix - 16-bit adc co nv e rs i o n s e q u e n ce cin0 cin1 cin2 cin3 cin4 cin5 cin6 cin7 06472-021 figure 23. cdc conversion stages the number of required conversion stages depends completely on the number of sensors attached to the AD7143. figure 24 shows how many conversion stages are required for each sensor, and how many inputs each sensor requires to the AD7143. buttons stage0 cdc stage0 cdc + ? stage1 8-element slider cdc + ? + ? stage1 + ? cdc AD7143 sequencer cdc stage2 + ? stage3 + ? cdc cdc stage4 + ? stage5 + ? cdc cdc stage6 + ? stage7 + ? cdc AD7143 sequencer src src s2 s3 s1 0 6472-022 figure 24. sequencer setup for sensors a button sensor generally requires one sequencer stage. however, it is possible to configure two button sensors to operate differentially for special applications where the user should not press both buttons simultaneously, such as a with rocker zoom switch on a digital camera. in this case, only one button from the pair is activated at a time; pressing both buttons together activates neither button. this example is shown in figure 24 for sensor buttons s2 and s3. a scroll bar or slider requires eight stages. the result from each stage is used by the host software to determine the users position on the scroll bar. the algorithm that performs this process is available from analog devices free of charge, upon signing a software license. scroll wheels also require eight stages. cdc conversion sequence time the time required for one complete measurement for all eight stages by the cdc is defined as the cdc conversion sequence time. the sequence_stage_num register and decimation register determine the conversion time as listed in table 8 . table 8. cdc conversion times for full power mode conversion time (ms) sequence_stage_num decimation = 128 decimation = 256 0 1.525 3.072 1 3.072 6.144 2 4.608 9.216 3 6.144 12.288 4 7.68 15.25 5 9.216 18.432 6 10.752 21.504 7 12.288 24.576 for example, while operating with a decimation rate of 128, if the sequence_stage_num register is set to 5 for the conversion of six stages in a sequence, the conversion sequence time is 9.216 ms. full power mode cdc conversion sequence time the full power mode cdc conversion sequence time for all eight stages is set by configuring the sequence_stage_num register and the decimation register as outlined in table 8 . figure 25 shows a simplified timing diagram of the full power cdc conversion time. the full power mode cdc conversion time t conv_fp is set using tabl e 8 . conversion sequence n conversion sequence n + 1 conversion sequence n + 2 cdc conversion t conv_fp 06472-023 figure 25. full power mode cdc conversion sequence time
AD7143 rev. 0 | page 16 of 56 low power mode cdc conversion sequence time with delay the frequency of each cdc conversion while operating in the low power automatic wake-up mode is controlled by using the lp_conv_delay register located at address 0x000[3:2], in addition to the registers listed in table 8 . this feature provides some flexibility for optimizing the conversion time to meet system requirements vs. AD7143 power consumption. for example, maximum power savings is achieved when the lp_conv_delay register is set to 3. with a setting of 3, the AD7143 automatically wakes up, performing a conversion every 800 ms. table 9. lp_conv_delay settings lp_conv_delay bits delay between conversions 00 200 ms 01 400 ms 10 600 ms 11 800 ms figure 26 shows a simplified timing example of the low power cdc conversion time. as shown, the low power cdc conversion time is set by t conv_fp and the lp_conv_delay register. conversion sequence n conversion sequence n + 1 cdc conversion lp_conv_delay t conv_lp t conv_fp 06472-024 figure 26. low power mode cdc conversion sequence time cdc conversion results certain high-resolution sensors require the host to read back the cdc conversion results for processing. the registers required for host processing are located in the bank 3 registers. the host processes the data readback from these registers using a software algorithm to determine position information. in addition to the results registers in the bank 3 registers, the AD7143 provides the 16-bit cdc output data directly starting at address 0x00b of bank 1. reading back the cdc 16-bit conversion data register allows for customer-specific application data processing.
AD7143 rev. 0 | page 17 of 56 noncontact proximity detection the AD7143 internal signal processing continuously monitors all capacitance sensors for noncontact proximity detection. this feature provides the ability to detect when a user is approaching a sensor, immediately disabling all internal calibration while the AD7143 is automatically configured to detect a valid contact. the proximity control register bits are described in table 10 . fp_proximity_cnt register bits and lp_proximity _cnt register bits control the length of the calibration disable period after proximity is detected in full power and low power modes. the calibration is disabled during this time and enabled again at the end of this period if the user is no longer approaching, or in contact with, the sensor. figure 27 and figure 28 show examples of how these registers are used to set the full and low power mode calibration disable periods. calibration disable period in full power mode = ( fp_proximity_cnt 16 time for one conversion sequence in full power mode ) calibration disable period in low power mode = ( lp_proximity_cnt 4 time for one conversion sequence in low power mode ) recalibration in certain situations, the proximity flag can be set for a long period, such as when a user hovers over a sensor for a long time. the environmental calibration on the AD7143 is suspended while the proximity is detected, but changes may occur to the ambient capacitance level during the proximity event. even when the user has left the sensor untouched, the proximity flag may still be set. this could occur if the user interaction creates some moisture on the sensor causing the new sensor value to be different from the expected value. in this case, the AD7143 automatically forces an internal recalibration. this ensures that the ambient values are recalibrated, regardless of how long the user hovers over a sensor. the AD7143 recalibrates automatically when the measured cdc value exceeds the stored ambient value by an amount determined by proximity_recal_lvl, for a set period know as the recalibration timeout. in full power mode, the recalibration timeout is controlled by fp_proximity_recal and in low power mode, it is controlled by lp_proxmty_recal. recalibration timeout in full power mode = fp_proximity_recal time for one conversion sequence in full power mode recalibration timeout in low power mode = lp_proximity_recal time taken for one conversion sequence in low power mode figure 29 and figure 30 show examples of using the fp_proximity_recal and lp_proximity_recal register bits to force a recalibration while operating in the full and low power modes. these figures show the result of a user approaching a sensor then leaving the sensor while the proximity detection remains active after the user discontinues contact with the sensor. this situation could occur if the user interaction created some moisture on the sensor causing the new sensor value to be different from the expected value. in this case, the internal recalibration is applied to automatically recalibrate the sensor. the forced recalibration event takes two interrupt cycles; therefore, it should not be set again during this interval. proximity sensitivity the fast filter in figure 31 is used to detect when some one is in close proximity to the sensor. two conditions set the internal proximity detection signal using comparator 1 and comparator 2. comparator 1 detects when a user is approaching a sensor. the proximity_detection_rate register controls the sensitivity of comparator 1. consider, for example, if the proximity_detection_rate is set to 4, the proximity 1 signal is set when the absolute difference between word1 and word3 exceeds four lsb codes. comparator 2 detects when a user hovers over a sensor or approaches a sensor very slowly. the proximity_recal_lvl register (address 0x003) controls the sensitivity of comparator 2. for example, if proximity_recal_lvl is set to 75, the proximity 2 signal is set when the absolute difference between the fast filter average value and the ambient value exceeds 75 lsb codes. table 10. proximity control registers (see figure 31 ) register length register address description fp_proximity_cnt 4 bits 0x002 [7:4] calibr ation disable time in full power mode lp_proximity_cnt 4 bits 0x002 [11:8] calibration disable time in low power mode fp_proximity_recal 8 bits 0x004 [9:0] full power mode proximity recalibration control lp_proximity_recal 6 bits 0x004 [15:10] low power mode proximity recalibration control proximity_recal_lvl 8 bits 0x003 [13:8] proximity recalibration level proximity_detection_rate 6 bits 0x003 [7:0] proximity detection rate
AD7143 rev. 0 | page 18 of 56 calibration enabled calibration disabled proximity detection (internal) calibration (internal) 12345678910111213141516 cdc conversion sequence (internal) user leaves sensor area here user approaches sensor here 17 18 19 20 21 22 23 24 t conv_fp t caldis 06472-025 figure 27. full power mode proximity detection example with fp_proximity_cnt = 1 notes 1. sequence conversion time t conv_lp = t conv_fp + lp_conv_delay. 2. proximity is set when user approaches the sensor at which time the internal calibration is disabled. 3. t caldis = ( t conv_lp lp_proximity_cnt 4). calibration enabled calibration disabled proximity detection (internal) calibration (internal) t caldis t conv_lp 12345678910111213141516 cdc conversion sequence (internal) user leaves senso r area here user approaches sensor here 17 18 19 20 21 22 23 24 06472-026 figure 28. low power mode proximity detection with lp_proximity_cnt = 4 and lp_conv_delay = 0 calibration enabled t recal_timeout 16 30 70 t conv_fp measured cdc value > stored ambient by proximity_recal _lvl recalibration timeout proximity detection (internal) calibration (internal) cdc conversion sequence (internal) recalibration counter (internal) user approaches sensor here user leaves sensor area here t caldis t recal calibration disabled notes 1. t caldis = t conv_fp fp_proximity_cnt 16. 2. t recal_timeout = t conv_fp fp_proximity_recal. 3. t recal = 2 t conv_fp . 06472-027 figure 29. full power mode proximity detection with forced reca libration example with fp_proximit_cnt = 1 and fp_proximity_reca l = 40 note that in figure 29 , the sequence conversion time, t conv_fp, is determined from table 8 .
AD7143 rev. 0 | page 19 of 56 calibration enabled t recal_timeout 16 30 70 t conv_fp measured cdc value > stored ambient by proximity_recal _lvl recalibration timeout proximity detection (internal) calibration (internal) cdc conversion sequence (internal) recalibration (internal) user approaches sensor here user leaves sensor area here t caldis t recal calibration disabled notes 1. sequence conversion time t conv_lp = t conv_fp + lp_conv_delay. 2. t caldis = t conv_lp lp_proximity_cnt 4. 3. t recal_timeout = t conv_fp lp_proximity_recal. 4. t recal = 2 t conv_lp . 06472-028 figure 30. low power mode proximity detection with forced recalibration example with lp_proximit_cnt = 4 and lp_proximity_recal = 10 ff_skip_cnt the proximity detection fast fifo is used by the on-chip logic to determine if proximity is detected. the fast fifo expects to receive samples from the converter at a set rate. using ff_skip_cnt normalizes the frequency of the samples going into the fifo, regardless of how many conversion stages are in a sequence. in register 0x02, bits[3:0] are the fast filter skip control, ff_skip_cnt. this value determines which cdc samples are not used (skipped) in the proximity detection fast fifo. determining the ff_skip_cnt value is required only once during the initial setup of the capacitance sensor interface. table 11 shows how ff_skip_cnt controls the update rate to the fast fifo. the recommended value for ff_skip_cnt when using all 12 conversion stages on the AD7143 is ff_skip_cnt = 0000 = no samples skipped slow fifo as shown in figure 31 , a number of fifos are implemented on the AD7143. these fifos are located in bank 3 of the on-chip memory. the slow fifos are used by the on-chip logic to monitor the ambient capacitance level from each sensor. avg_fp_skip and avg_lp_skip in register 0x001, bits[13:12] are the slow fifo skip control for full power mode, avg_fp_skip. bits[15:14] in the same register are the slow fifo skip control for low power mode, avg_lp_skip. these values determine which cdc samples are not used (skipped) in the slow fifo. changing theses values slows down or speeds up the rate at which the ambient capacitance value tracks the measured capacitance value read by the converter. slow fifo update rate in full power mode is equal to avg_fp_skip [(3 decimation rate ) ( sequence_stage_num +1) ( ff_skip_cnt +1) 4 10 -7 ] slow fifo update rate in low power mode is equal to ( avg_lp_skip +1) [(3 decimation rate ) sequence_stage_num +1) ( ff_skip_cnt +1) 4 10 -7 ] / [( ff_skip_cnt +1)+ lp_conv_delay ] the slow fifo is used by the on-chip logic to track the ambient capacitance value. the slow fifo expects to receive samples from the converter at a rate of 33 ms to 40 ms. avg_fp_skip and avg_lp_skip are used to normalize the frequency of the samples going into the fifo, regardless of how many conversion stages are in a sequence. determining the avg_fp_skip and avg_lp_skip value is only required once during the initial setup of the capacitance sensor interface. recommended values for these settings when using all 12 conversion stages on the AD7143 are avg_fp_skip = 00 = skip 3 samples avg_lp_skip = 00 = no samples skipped slow_filter_update_lvl the slow_filter_update_lvl controls whether or not the most recent cdc measurement goes into the slow fifo (slow filter). the slow filter is updated when the difference between the current cdc value and last value pushed into the slow fifo is greater than slow_filter_update_lvl. this variable is in ambient control register 1, at address 0x003.
AD7143 rev. 0 | page 20 of 56 table 11. ff_skip_cnt settings fast fifo update rate ff_skip_cnt decimation = 128 decimation = 256 0 1.525 (sequence_stage_num + 1) ms 3.072 (sequence_stage_num + 1) ms 1 3.072 (sequence_stage_num + 1) ms 6.144 (sequence_stage_num + 1) ms 2 4.608 (sequence_stage_num + 1) ms 9.216 (sequence_stage_num + 1) ms 3 6.144 (sequence_stage_num + 1) ms 12.288 (sequence_stage_num + 1) ms 4 7.68 (sequence_stage_num + 1) ms 15.25 (sequence_stage_num + 1) ms 5 9.216 (sequence_stage_num + 1) ms 18.432 (sequence_stage_num + 1) ms 6 10.752 (sequence_stage_num + 1) ms 21.504 (sequence_stage_num + 1) ms 7 12.288 (sequence_stage_num + 1) ms 24.576 (sequence_stage_num + 1) ms 8 13.824 (sequence_stage_num + 1) ms 27.648 (sequence_stage_num + 1) ms 9 15.25 (sequence_stage_num + 1) ms 30.72 (sequence_stage_num + 1) ms 10 16.896 (sequence_stage_num + 1) ms 33.792 (sequence_stage_num + 1) ms 11 18.432 (sequence_stage_num + 1) ms 25.864 (sequence_stage_num + 1) ms 12 19.968 (sequence_stage_num + 1) ms 39.925 (sequence_stage_num + 1) ms 13 21.504 (sequence_stage_num + 1) ms 43.008 (sequence_stage_num + 1) ms 14 23.04 (sequence_stage_num + 1) ms 46.08 (sequence_stage_num + 1) ms 15 24.576 (sequence_stage_num + 1) ms 49.152 (sequence_stage_num + 1) ms
AD7143 rev. 0 | page 21 of 56 notes 1. slow filter en is set and sw1 is closed when |stage_sf_ word 0 to stage_sf_word 1 | exceeds the value programmed in the slow_filter_update_lvl register providing proximity is not set. 2. proximity 1 is set when |stage_ff_ word 0 to stage_ff_word 3 | exceeds the value programmed in the proximity_detection_rate register. 3. proximity 2 is set when | average?ambient | exceeds the value programmed in the proximity_recal_lvl register. 4. description of comparator functions: comparator 1: used to detect when a user is approaching or leaving a sensor. comparator 2: used to detect when a user is hovering over a sensor, or approaching a sensor very slowly. also used to detect if the sensor ambient level has changed as a result of the user interaction. for example, humidity or dirt left behind on sensor. comparator 3: used to enable the slow filter update rate. the slow filter is updated when slow filter en is set and proximity is not set. bank 3 registers sw1 proximity slow_filter_en stage_sf_word0 stage_sf_word1 stage_sf_word2 stage_sf_word3 stage_sf_word4 stage_sf_word5 stage_sf_word6 stage_sf_word7 stage_ff_word0 stage_ff_word1 stage_ff_word2 stage_ff_word3 stage_ff_word4 stage_ff_word5 stage_ff_word6 stage_ff_word7 8 7 word( n ) n = 0 comparator 3 word0 to word1 slow_filter_update_lvl register 0x003 stage_sf_ambient bank 3 registers stage_ff_avg bank 3 registers 16 cdc comparator 1 |word0 to word3| proximity_detection_rate register 0x003 comparator 2 |average?ambient| proximity 2 proximity_recal_lvl register 0x003 proximity 1 proximity lp_proximity_cnt register 0x002 fp_proximity_cnt register 0x002 lp_proximity_recal register 0x004 fp_proximity_recal register 0x004 proximity timing control logic cdc output code time ambient value stage_sf_wordx stage_ff_wordx sensor contact 0 6472-029 figure 31. AD7143 proximity detection and environmental calibration bank 3 registers stage_max_word0 stage_max_word1 stage_max_word2 stage_max_word3 stage_min_word0 stage_min_word1 stage_min_word2 stage_min_word3 stage_max_avg bank 3 registers stage_max_temp bank 3 registers stage_high_threshold bank 3 registers stage_min_avg bank 3 registers stage_min_avg bank 3 registers stage_low_threshold bank 3 registers bank 3 registers max level detection logic min level detection logic 16 - 16-bit cdc 06472-048 figure 32. AD7143 maximum and minimum level detection logic
AD7143 rev. 0 | page 22 of 56 environmental calibration the AD7143 provides on-chip capacitance sensor calibration to automatically adjust for environmental conditions that have an effect on the capacitance sensor ambient levels. capacitance sensor output levels are sensitive to temperature, humidity, and in some cases, dirt. the AD7143 achieves optimal and reliable sensor performance by continuously monitoring the cdc ambient levels and correcting for any changes by adjusting the stage_high_threshold and stage_low_threshold register values as described in equation 1 and equation 2. the cdc ambient level is defined as the capacitance sensor output level during periods when the user is not approaching or in contact with the sensor. the compensation logic runs automatically on every conversion after configuration when the AD7143 is not being touched. this allows the AD7143 to account for rapidly changing environmental conditions. the ambient compensation control registers located at address 0x002, address 0x003 and address 0x004 give the host access to general setup and controls for the compensation algorithm. the ram stores the compensation data for each conversion stage, as well as setup information specific to each stage. figure 33 shows an example of an ideal capacitance sensor behavior where the cdc ambient level remains constant regardless of the environmental conditions. the cdc output shown is for a pair of differential button sensors, where one sensor caused an increase, and the other a decrease in measured capacitance when activated. the positive and negative sensor threshold levels are calculated as a percentage of the stage_offset_high and stage_offset_low values based on the threshold sensitivity settings and the ambient value. these values for this example are sufficient to detect a sensor contact, resulting with the AD7143 asserting the int output when the threshold levels are exceeded. cdc output codes t stage_low_threshold stage_high_threshold cdc ambient value changing environmental conditions sensor 1 int asserted sensor 2 int asserted 06472-030 figure 33. ideal sensor behavior with a constant ambient level capacitance sensor behavior without calibration figure 34 shows the typical behavior of a capacitance sensor with no applied calibration. this figure shows ambient levels drifting over time as environmental conditions change. the ambient level drift has resulted in the detection of a missed user contact on sensor 2. this is a result of the initial stage_low_threshold remaining constant while the ambient levels drifted upward beyond the detection range. the capacitance sensor behavior with calibration section describes how the AD7143 adaptive calibration algorithm prevents errors such as this from occurring. cdc output codes t ccdc ambient value drifting changing environmental conditions stage_high_threshold stage_low_threshold sensor 1 int asserted sensor 2 int not asserted 06472-031 figure 34. typical sensor behavior without calibration applied
AD7143 rev. 0 | page 23 of 56 capacitance sensor behavior with calibration the AD7143 on-chip adaptive calibration algorithm prevents sensor detection errors, such as the one shown in figure 34 . this is achieved by monitoring the cdc ambient levels and readjusting the initial stage_offset_high and stage_offset_low values according to the amount of ambient drift measured on each sensor. the internal stage_high_threshold and stage_low_threshold values, shown in equation 1 and equation 2, are automatically updated based on the new stage_offset_high and stage_offset_low values. this closed-loop routine ensures the reliability and repeatable operation of every sensor connected to the AD7143 under dynamic environmental conditions. figure 35 shows a simplified example of how the AD7143 applies the adaptive calibration process resulting in no interrupt errors under changing cdc ambient levels due to environmental conditions. cdc output codes t sensor 1 int asserted 1 2 3 4 5 6 stage_high_threshold (post calibrated register value) changing environmental conditions 1 initial stage_offset_high register value. 2 post calibrated register stage_high_threshold. 3 post calibrated register stage_high_threshold. 4 initial stage_low_threshold. 5 post calibrated register stage_low_threshold. 6 post calibrated register stage_low_threshold. cdc ambient value drifting stage_low_threshold (post calibrated register value) sensor 2 int asserted 06472-032 figure 35. typical sensor behavior with calibration applied on the data path on-chip logic stage high threshold calculation snsitivit thrshold pos high offst stag high offst stag high offst stag ambint sfstag thrshold high stag _ _ 16 4 __ __ 4 __ __ __ ? + + = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (1) on-chip logic stage low threshold calculation snsitivit thrshold ng low offst stag low offst stag low offst stag ambint sfstag thrshold low stag _ _ 16 4 __ __ 4 __ __ __ ? + + = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (2)
AD7143 rev. 0 | page 24 of 56 table 12. additional information about environmen tal calibration and adaptive threshold registers register location description neg_threshold_sensitivity bank 2 used in equation 2. this value is programmed once at start up. neg_peak_detect bank 2 used by internal adaptive threshold logi c only. the neg_peak_detect is set to a percentage of the difference between the ambient cdc value and the minimum average cdc value. if the output of the cdc gets within the neg_peak_detect percentage of the minimum average, only then is the minimum average value updated. pos_threshold_sensitivity bank 2 used in equation 1. this value is programmed once at startup. pos_peak_detect bank 2 used by internal adaptive threshold logic only. the pos_peak_detect is set to a percentage of the difference between the ambient cdc value, and the maximum average cdc value. if the output of the cdc gets within the pos_peak_detect percentage of the minimum average, only then is the maximum average value updated. stage_offset_low bank 2 used in equation 2. an initial value (based on sensor characterization) is programmed into this register at startup. the AD7143 on-chip calibration algorithm automatically updates this register based on the amount of sensor drift due to changing ambient conditions. set to 80% of the stage_offset_low_clamp value. stage_offset_high bank 2 used in equation 1. an initial value (based on sensor characterization) is programmed into this register at startup. the AD7143 on-chip calibration algorithm automatically updates this register based on the amount of sensor drift due to changing ambient conditions. set to 80% of the stage_offset_high_clamp value. stage_offset_high_clamp bank 2 used by internal environmen tal calibration and adaptive threshold algorithms only. an initial value (based on sensor characteriza tion) is programmed into this register at startup. the value in this register prevents a user from causing a sensor output value to exceed the expected nominal value. set to the maximum expected sensor response, maximum change in cdc output code. stage_offset_low_clamp bank 2 used by internal environmenta l calibration and adaptive threshold algorithms only. an initial value (based on sensor characteriza tion) is programmed into this register at startup. the value in this register prevents a user from causing a sensor output value to exceed the expected nominal value. set to the minimum expected sensor response, minimum change in cdc output code . stage_sf_ambient bank 3 used in equation 1 and equation 2. this is the ambient sensor output, when the sensor is not touched, as calcul ated using the slow fifo. stage_high_threshold bank 3 equation 1 value. stage_low_threshold bank 3 equation 2 value.
AD7143 rev. 0 | page 25 of 56 adaptive threshold and sensitivity the AD7143 provides an on-chip self-learning adaptive threshold and sensitivity algorithm. this algorithm continu- ously monitors the output levels of each sensor and automatically rescales the threshold levels proportionally to the sensor area covered by the user. as a result, the AD7143 maintains optimal threshold and sensitivity levels for all types of users regardless of their finger sizes. the threshold level is always referenced from the ambient level and is defined as the cdc converter output level that must be exceeded for a valid sensor contact. the sensitivity level is defined as how sensitive the sensor is before a valid contact is registered. figure 36 provides an example of how the adaptive threshold and sensitivity algorithm works. the positive and negative sensor threshold levels are calculated as a percentage of the stage_offset_high and stage_offset_low values based on the threshold sensitivity settings and the ambient value. on configuration, initial estimates are supplied for both stage_offset_high and stage_offset_low after which the calibration engine automatically adjusts the stage_high_threshold and stage_low_threshold values for sensor response. reference a in figure 36 shows an under sensitive threshold level for a small finger user, demonstrating the disadvantages of a fixed threshold level. by enabling the adaptive threshold and sensitivity algorithm, the positive and negative threshold levels are determined by the pos_threshold_sensitivity and neg_threshold_sensitivity register values and the most recent average maximum sensor output value. these registers can be used to select 16 different positive and negative sensitivity levels ranging between 25% and 95.32% of the most recent average maximum output level referenced from the ambient value. the smaller the sensitivity percentage setting, the easier it is to trigger a sensor activation. reference b shows that the positive adaptive threshold level is set at almost mid- sensitivity with a 62.51% threshold level by setting pos_threshold_sensitivity = 1000. figure 36 also provides a similar example for the negative threshold level with neg_threshold_sensitivity = 0001. ambient level cdc output codes average max value stage_offset_high 25% 95.32% 62.51% = pos adaptive threshold level 25% 62.51% = pos adaptive threshold level 95.32% neg adaptive threshold level = 39.08% 25% 95.32% 25% 95.32% sensor contacted by small finger a verage max value stage_offset_low neg adaptive threshold level = 39.08% sensor contacted by large finger stage_offset_high is updated stage_offset_high is updated here stage_offset_low is updated here stage_offset_lo w is updated here a b 0 6472-033 figure 36. threshold sensitivity example with pos_threshold_ sensitivity = 1000 and neg_th reshold_sensitivity = 0011
AD7143 rev. 0 | page 26 of 56 interrupt output the AD7143 has an interrupt output that triggers an interrupt service routine on the host processor. the int signal is on pin 14, and is an open-drain output. there are two types of interrupt events on the AD7143: a cdc conversion complete interrupt and a sensor touch interrupt. each interrupt has enable and status registers described in table 13 . the conversion complete and sensor threshold interrupts can be enabled on a per conversion stage basis. the status registers indicate what type of interrupt triggered the int pin. status registers are cleared, and the int signal is reset high, during a read operation of the interrupt status registers. the signal returns high as soon as the read address has been set up. cdc conversion complete interrupt the AD7143 interrupt signal asserts low to indicate the completion of a conversion stage, and new conversion result data is available in the registers. the interrupt can be independently enabled for each conversion stage. each conversion stage complete interrupt can be enabled via the stage_complete_en register (address 0x007). this register has a bit that corresponds to each conversion stage. setting this bit to 1 enables the interrupt for that stage. clearing this bit to 0 disables the conversion complete interrupt for that stage. figure 38 shows an end of conversion interrupt timing with the stage0 interrupt enabled. in normal operation, the AD7143s interrupt is enabled only for the last stage in a conversion sequence as shown in figure 38 . register 0x00a is the conversion complete interrupt status register. each bit in this register corresponds to a conversion stage. if a bit is set, it means that the conversion complete interrupt for the corresponding stage was triggered. this register is cleared on a read, provided the underlying condition that triggered the interrupt has gone away. sensor touch interrupt the sensor touch interrupt mode is implemented when the host processor requires an interrupt only when a sensor is contacted. configuring the AD7143 into this mode results in the interrupt being asserted when the user makes contact with the sensor and again when the user lifts off the sensor. the second interrupt is required to alert the host processor that the user is no longer contacting the sensor. the registers located at address 0x005 and address 0x006 are used to enable the interrupt output for each stage. the registers located at address 0x008 and address 0x009 are used to read back the interrupt status for each stage. figure 37 shows the interrupt output timing during contact with one of the sensors connected to stage0 while operating in the sensor touch interrupt mode. for a low limit configuration, the interrupt output is asserted as soon as the sensor is contacted and again after the user has stopped contacting the sensor. note that the interrupt output remains low until the host processor reads back the interrupt status registers located at address 0x008 and address 0x009. the interrupt output is asserted when there is a change in the threshold status bits. this could indicate that a user is now touching the sensor(s) for the first time, the number of sensors being touched has changed, or the user is no longer touching the sensor(s). reading the status bits in the interrupt status register shows the current sensor activations. 4 2 conversion stage serial read back int output 3 1 stage1 stage0 finger on sensor finger off sensor 1 user touching down on sensor. 2 address 0x008 read back to clear interrupt. 3 user lifting off of sensor. 4 address 0x008 read back to clear interrupt. 06472-034 figure 37. example of sensor touch interrupt
AD7143 rev. 0 | page 27 of 56 table 13. interrupt mode registers interrupt mode interrupt enable register address interrupt status register address notes sensor touch interrupt asserted when the user contacts a sensor. see figure 37 . low 0x005 0x008 enable for the cin inputs connected to the cdc positive stage. high 0x006 0x009 enable for the cin inputs connected to the cdc negative stage. cdc conversion complete 0x007 0x00a continuous interrupt at the end of each stagex that is enabled. 2 1 c onversions serial reads stage0 stage1 stage2 stage3 stage4 stage5 stage6 stage7 stage8 stage9 stage10 stage11 stage0 stage1 notes 1. this is an example of a cdc conversion complete interrupt. 2. this timing example shows that the interrupt output has been enabled to be asserted at the end of a conversion cycle for stage0 only. 3. stagex configuration programming notes for stage0, stage5, and stage9 (x = 0, 5, 9) stagex_low_int_en (address 0x005) = 0 stagex_high_int_en (address 0x006) = 0 stagex_complete_en (address 0x007) = 1 int 06472-035 figure 38. example of configuring the regist ers for end of conver sion interrupt setup
AD7143 rev. 0 | page 28 of 56 serial interface the AD7143 is available with a fixed address i 2 c-compatible interface. i 2 c compatible interface the AD7143 supports the industry standard 2-wire i 2 c serial interface protocol. the two wires associated with the i 2 c timing are the sclk and the sda inputs. the sda is an i/o pin that allows both register write and register readback operations. the AD7143 is always a slave device on the i 2 c serial interface bus. the AD7143 has a single fixed 7-bit device address, address 0101 110. the AD7143 responds when the master device sends its device address over the bus. the AD7143 cannot initiate data tr ansfers on the bus. table 14. AD7143 i 2 c fixed device address dev a6 dev a5 dev a4 dev a3 dev a2 dev a1 dev a0 0 1 0 1 1 1 0 data transfer data is transferred over the i 2 c serial interface in 8-bit bytes. the master initiates a data transfer by establishing a start con- dition, defined as a high-to-low transition on the serial data line, sda, while the serial clock line, sclk, remains high. this indicates that an address/data stream follows. all slave peripherals connected to the serial bus respond to the start condition and shift in the next eight bits, consisting of a 7-bit address (msb first) plus an r/ w bit that determines the direction of the data transfer. the peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the ninth clock pulse. this is known as the acknowledge bit. all other devices on the bus now remain idle while the selected device waits for data to be read from, or written to it. if the r/ w bit is a 0, the master writes to the slave device. if the r/ w bit is a 1, the master reads from the slave device. data is sent over the serial bus in a sequence of nine clock pulses, eight bits of data followed by an acknowledge bit from the slave device. transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, since a low-to-high transition when the clock is high can be interpreted as a stop signal. the number of data bytes transmitted over the serial bus in a single read or write operation is limited only by what the master and slave devices can handle. when all data bytes are read or written, a stop condition is established. a stop condition is defined by a low-to-high transition on sda while sclk remains high. if the AD7143 encounters a stop condition, it returns to its idle condition, and the address pointer register resets to address 0x00. sda dev a6 dev a5 dev a4 r/w a7 a6 sclk dev a3 a1 a0 1 26 234 17 18 19 20 25 dev a2 dev a1 dev a0 ack a15 a14 11 16 5678 910 start AD7143 device address a9 a8 register address [a15:a8] register address [a7:a0] ack d15 d14 d9 d8 35 27 28 29 34 3736 43 38 44 d1 d0 d7 d6 ack ack 45 46 ack stop dev a6 dev a5 dev a4 123 start t 8 t 7 t 6 t 5 t 4 t 2 t 1 t 3 AD7143 device address notes 1. a start condition at the beginning is defined as a high-to-low transition on sda while sclk remains high. 2. a stop condition at the end is defined as a low-to-high transition on sda while sclk remains high. 3. 7-bit device address [dev a6:dev a0] = [0 1 0 1 1 1 0]. 4. 16-bit register address [a15:a0] = [x, x, x, x, x, x, a9, a8 , a7, a6, a5, a4, a3, a2, a1, a0], where x are don?t care bits. 5. register address [a15:a8] and register address [a7:a0] are always separated by a low ack bit. 6. register data [d15:d8] and register data [d7:d0] are always separated by a low ack bit. register data [d15:d8] register data [d7:d0] 0 6472-036 figure 39. example of i 2 c timing for single register write operation
AD7143 rev. 0 | page 29 of 56 writing data over the i 2 c bus the process for writing to the AD7143 over the i 2 c bus is shown in figure 39 and figure 41 . the device address is sent over the bus followed by the r/ w bit set to 0. this is followed by two bytes of data that contain the 10-bit address of the internal data register to be written. the following bit map shows the upper register address bytes. note that bit 7 to bit 2 in the upper address byte are dont care bits. the address is contained in the 10 lsbs of the register address bytes. msb lsb 7 6 5 4 3 2 1 0 x x x x x x register address bit 9 register address bit 8 the following bit map shows the lower register address bytes. msb lsb 7 6 5 4 3 2 1 0 reg. addr. reg. addr. reg. addr. reg. addr. reg. addr. reg. addr. reg. addr. reg. addr. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 the third data byte contains the 8 msbs of the data to be written to the internal register. the fourth data byte contains the 8 lsbs of data to be written to the internal register. the AD7143 address pointer register automatically increments after each write. this allows the master to sequentially write to all registers on the AD7143 in the same write transaction. however, the address pointer register does not wrap around after the last address. any data written to the AD7143 after the address pointer has reached its maximum value is discarded. all registers on the AD7143 are 16-bit. two consecutive 8-bit data bytes are combined and written to the 16-bit registers. to avoid errors, all writes to the device must contain an even number of data bytes. to finish the transaction, the master generates a stop condition on sda, or generates a repeat start condition if the master is to maintain control of the bus. reading data over the i 2 c bus to read from the AD7143, the address pointer register must first be set to the address of the required internal register. the master performs a write transaction, and writes to the AD7143 to set the address pointer. the master then outputs a repeat start condition to keep control of the bus, or, if this is not possible, ends the write transaction with a stop condition. a read transaction is initiated, with the r/ w bit set to 1. the AD7143 supplies the upper eight bits of data from the addressed register in the first readback byte, followed by the lower eight bits in the next byte. this is shown in figure 40 and figure 41 . because the address pointer automatically increases after each read, the AD7143 continues to output readback data until the master puts a no acknowledge and stop condition on the bus. if the address pointer reaches its maximum value, and the master continues to read from the part, the AD7143 repeatedly sends data from the last register addressed.
AD7143 rev. 0 | page 30 of 56 sda dev a6 dev a5 dev a4 r/w a7 a6 sclk dev a3 a1 a0 1 26 234 17 18 19 20 25 dev a2 dev a1 dev a0 ack a15 a14 11 16 5678 910 AD7143 device address a9 a8 register address [a15:a8] register address [a7:a0] ack 35 28 30 34 3736 44 38 45 d1 d0 d7 d6 sr ack 46 p dev a6 dev a5 dev a4 123 t 8 t 7 t 6 t 5 t 4 t 2 t 1 t 3 AD7143 device address ack 27 AD7143 device address dev a6 dev a5 dev a1 dev a0 r/w 29 39 35 28 30 34 3736 44 38 45 d1 d0 d7 d6 s ack 46 p t 5 t 4 AD7143 device address dev a6 dev a5 dev a1 dev a0 r/w 29 39 p using repeated start separate read and w rite transactions ack ack start register data [d7:d0] register data [d7:d0] notes 1. a start condition at the beginning is defined as a high-to-low transition on sda while sclk remains high. 2. a stop condition at the end is defined as a low-to-high transition on sda while sclk remains high. 3. the master generates the ack at the end of the readback to signal that it does not want additional data. 4. 7-bit device address [dev a6:dev a0] = [0 1 0 1 1 1 0]. 5. 16-bit register address[a15:a0] = [x, x, x, x, x, x, a9, a8, a7, a6, a5, a4, a3, a2, a1, a0], where the upper lsb xs are don ?t care bits. 6. register addr ess [a15:a8] and register address [a7:a0] are always separated by low ack bits. 7. register data [d15:d8] and register data [d7:d0] are always separated by a low ack bit. 8. the r/w bit is set to a1 to indicate a readback operation. 06472-037 figure 40. example of i 2 c timing for single regi ster readback operation ack write output from master s p p ack ack = no acknowledge bit ack ack w ack ack ack ack read (using repeated start) s ack ack w ack ack r sr p ack ack read (write transaction sets up register addr ess) s ack ack w ack ack r p s ack ack output from AD7143 s = start bit p = stop bit sr = repeated start bit ack = acknowledge bit 7-bit device address register addr [15:8] register addr [7:0] write data high byte [15:8] write data low byte [7:0] write data high byte [15:8] write data low byte [7:0] read data high byte [15:8] read data low byte [7:0] read data high byte [15:8] read data low byte [7:0] 6-bit device address register addr low byte register addr high byte 7-bit device address read data low byte [7:0] read data high byte [15:8] read data low byte [7:0] read data high byte [15:8] 6-bit device address register addr low byte register addr high byte 7-bit device address 0 6472-038 figure 41. example of sequential i 2 c write and readback operation
AD7143 rev. 0 | page 31 of 56 pcb design guidelines capacitive sensor board me chanical specifications table 15. parameter symbol min typ max unit distance from edge of any sensor to edge of metal object d 1 1.0 mm distance between sensor edges 1 d 2 = d 3 = d 4 0 mm distance between bottom of sensor board and controller board or metal casing 2 (4-layer, 2-layer, and flex circuit) d 5 1.0 mm 1 the distance is dependent on the application and the positioning of the switches relative to each other and with respect to th e users finger posi tioning and handling. adjacent sensors, with 0 minimum space betw een them, are impleme nted differentially. 2 the 1.0 mm specification is meant to prev ent direct sensor board contact with any co nductive material. this specification does not guarantee no emi coupling from the controller board to the sensors. address potential emi coupling issues by placing a grounded metal shield between the capac itive sensor board and the main controller board as shown in figure 44. slider buttons capacitive sensor printed circuit d 1 d 3 d 4 8-way switch metal object d 2 06472-039 figure 42. capacitive sensor board mechanicals top view d 5 capacitive sensor board grounded metal shield controller printed circuit board or metal casing 06472-040 figure 43. capacitive sensor board mechanicals side view d 5 capacitive sensor board controller printed circuit board or metal casing 06472-041 figure 44. capacitive sensor board with grounded shield chip scale packages the lands on the chip scale package (cp-16-13) are rectangular. the printed circuit board pad for these should be 0.1 mm longer than the package land length, and 0.05 mm wider than the package land width. center the land on the pad to maximize the solder joint size. the bottom of the chip scale package has a central thermal pad. the thermal pad on the printed circuit board should be at least as large as this exposed pad. to avoid shorting, provide a clearance of at least 0.25 mm between the thermal pad and the inner edges of the land pattern on the printed circuit board. thermal vias can be used on the printed circuit board thermal pad to improve thermal performance of the package. if vias are used, they should be incorporated in the thermal pad at a 1.2 mm pitch grid. the via diameter should be between 0.3 mm and 0.33 mm, and the via barrel should be plated with 1 oz. copper to plug the via. connect the printed circuit board thermal pad to gnd.
AD7143 rev. 0 | page 32 of 56 power-up sequence when the AD7143 is powered up, the following sequence is recommended when initially developing the AD7143 and host c serial interface: 1. turn on the power supplies to the AD7143. 2. write to the bank 2 registers at address 0x080 through address 0x0df. these registers are contiguous, so a sequential register write sequence can be applied. note: the bank 2 register values are unique for each application. register values are provided by analog devices after the sensor board has been developed. 3. write to the bank 1 registers at address 0x000 through address 0x007 as outlined below. these registers are contiguous so a sequential register write sequence can be applied caution: at this time, address 0x001 must remain set to default value 0x0000 during this contiguous write operation. register values: address 0x000 = 0x00b2 address 0x001 = 0x0000 address 0x002 = 0x0690 address 0x003 = 0x0664 address 0x004 = 0x290f address 0x005 = 0x0000 address 0x006 = 0x0000 address 0x007 = 0x0001 (the AD7143 interrupt is asserted approximately every 25 ms.) 4. write to the bank 1 register, address 0x001 = 0x0fff. 5. read back the corresponding interrupt status register at address 0x008, address 0x009, or address 0x00a. this is determined by the interrupt output configuration as explained in the interrupt output section. note: the specific registers required to be readback depend on each application. analog devices provides this information after the sensor board has been developed. 6. repeat step 5 each time int is asserted. first conversion sequence conversion stage 0 conversion stages disabled 1 2 3 4 5 6 7 8 9 10 11 0 1 2 910110 1 2 910110 1 second conversion sequence third conversion sequence 0 6472-042 power host serial interface AD7143 int figure 45. recommended start-up sequence
AD7143 rev. 0 | page 33 of 56 typical application circuits sda 0.1f 10nf sclk sensor pcb scroll wheel 1cin2 2cin3 3cin4 4cin5 11 vdrive 12 sda 10 gnd 9 vcc 6 c i n 7 5 c i n 6 7 c s h i e l d 8 s r c 1 5 c i n 0 1 6 c i n 1 1 4 i n t AD7143 1 3 s c l k v drive int optional i 2 c interface voltage (1.65v to 3.6v) vcc 2.7v to 3.6v 1f to 10f (optional) v host recommended to connect flooded plane around sensors to ground host with i 2 c interface 2.2k ? 2.2k ? 2.2k ? 0 6472-043 figure 46. typical application circuit with i 2 c interface
AD7143 rev. 0 | page 34 of 56 register map the AD7143 address space is divided into three different register banks, referred to as bank 1, bank 2, and bank 3. figure 47 illustrates the division of these three banks. bank 1 registers contain control registers, cdc conversion control registers, interrupt enable registers, interrupt status registers, cdc 16-bit conversion data registers, device id registers, and proximity status registers. bank 2 registers contain the configuration registers used for uniquely configuring the cin inputs for each conversion stage. initialize the bank 2 configuration registers immediately after power-up to obtain valid cdc conversion result data. bank 3 registers contains the results of each conversion stage. these registers automatically update at the end of each conversion sequence. although these registers are primarily used by the AD7143 internal data processing, they are accessible by the host processor for additional external data processing, if desired. default values are undefined for bank 2 registers and bank 3 registers until after power up and configuration of the bank 2 registers. register bank 1 addr 0x000 addr 0x018 addr 0x001 addr 0x005 addr 0x008 addr 0x00b addr 0x017 addr 0x013 addr 0x7f0 register bank 2 addr 0x080 addr 0x0b8 addr 0x088 addr 0x090 addr 0x098 addr 0x0a0 addr 0x0a8 addr 0x0b0 register bank 3 addr 0x0e0 addr 0x0b8 addr 0x088 addr 0x090 addr 0x098 addr 0x0a0 addr 0x0a8 addr 0x0b0 addr 0x042 addr 0x043 invalid do not access 24 registers proximity status register invalid do not access device id register cdc 16-bit conversion data (8 registers) interrupt status (3 registers) interrupt enable (3 registers) calibration and set up (4 registers) set up control (1 register) 64 registers 288 registers stage7 configuration (8 registers) stage6 configuration (8 registers) stage5 configuration (8 registers) stage4 configuration (8 registers) stage3 configuration (8 registers) stage2 configuration (8 registers) stage1 configuration (8 registers) stage0 configuration (8 registers) stage7 results (36 registers) stage6 results (36 registers) stage5 results (36 registers) stage4 results (36 registers) stage3 results (36 registers) stage2 results (36 registers) stage1 results (36 registers) stage0 results (36 registers) unused (4 registers) 06472-044 figure 47. layout of bank 1 registers, bank 2 registers, and bank 3 registers
AD7143 rev. 0 | page 35 of 56 detailed register descriptions bank 1 registers all addresses and default values are expressed in hexadecimal format. table 16. pwr_control register address data bit default type name description [1:0] 0 r/w power_mode operating modes 00 = full power mode (normal operation, cdc conversions approximately every 25 ms) 01 = full shutdown mode (no cdc conversions) 10 = low power mode (automatic wake-up operation) 11 = full shutdown mode (no cdc conversions) [3:2] 0 lp_conv_delay low power mode conversion delay 00 = 200 ms 01 = 400 ms 10 = 600 ms 11 = 800 ms [7:4] 0 sequence_stage_num number of stages in sequence (n + 1) 0000 = 1 conversion stage in sequence 0001 = 2 conversion stages in sequence maximum value = 1011 = 12 conversion stages per sequence [9:8] 0 decimation adc decimation factor 00 = decimate by 256 01 = decimate by 128 10 = do not use this setting 11 = do not use this setting [10] 0 sw_reset software reset control (self-clearing) 1 = resets all registers to default values [11] 0 int_pol interrupt polarity control 0 = active low 1 = active high [12] 0 excitation_source excitation source control for pin 15 0 = enable output 1 = disable output [13] 0 unused set unused register bits = 0 0x000 [15:14] 0 cdc_bias cdc bias current control 00 = normal operation 01 = normal operation + 20% 10 = normal operation + 35% 11 = normal operation + 50%
AD7143 rev. 0 | page 36 of 56 table 17. stage_cal_en register address data bit default type name description [0] 0 r/w stage0_cal_en stage0 calibration enable 0 = disable 1 = enable [1] 0 stage1_cal_en stage1 calibration enable 0 = disable 1 = enable [2] 0 stage2_cal_en stage2 calibration enable 0 = disable 1 = enable [3] 0 stage3_cal_en stage3 calibration enable 0 = disable 1 = enable [4] 0 stage4_cal_en stage4 calibration enable 0 = disable 1 = enable [5] 0 stage5_cal_en stage5 calibration enable 0 = disable 1 = enable [6] 0 stage6_cal_en stage6 calibration enable 0 = disable 1 = enable [7] 0 stage7_cal_en stage7 calibration enable 0 = disable 1 = enable [11:8] 0 unused set unused register bits = 0 [13:12] 0 avg_fp_skip full power mode skip control 00 = skip 3 samples 01 = skip 7 samples 10 = skip 15 samples 11 = skip 31 samples 0x001 [15:14] 0 avg_lp_skip low power mode skip control 00 = use all samples 01 = skip 1 sample 10 = skip 2 samples 11 = skip 3 samples
AD7143 rev. 0 | page 37 of 56 table 18. amb_comp_ctrl0 register address data bit default type name description [3:0] 0 r/w ff_skip_cnt fast filter skip control (n+1) 0000 = no sequence of results are skipped 0001 = one sequence of results is skipped for every one allowed into fast fifo 0010 = two sequences of results are skipped for every one allowed into fast fifo 1011 = maximum value = 12 sequences of results are skipped for every one allowed into fast fifo [7:4] f fp_proximity_cnt full power mode proximity period [11:8] f lp_proximity_cnt low power mode proximity period [13:12] 0 pwr_down_timeout full power to low power mode time out control 00 = 1.25 (fp_proximity_cnt) 01 = 1.50 (fp_proximity_cnt) 10 = 1.75 (fp_proximity_cnt) 11 = 2.00 (fp_proximity_cnt) [14] 0 forced_cal forced calibration control 0 = normal operation 1 = forces all conversion stages to recalibrate 0x002 [15] 0 conv_reset conversion reset control (self-clearing) 0 = normal operation 1 = resets the conversion sequence back to stage0 table 19. amb_comp_ctrl1 register address data bit default type name description [7:0] 64 proximity_recal_lvl proximity recalibration level [13:8] 1 proximity_detection_rate proximity detection rate 0x003 [15:14] 0 r/w slow_filter_update_lvl slow filter update level table 20. amb_comp_ctrl2 register address data bit default type name description 0x004 [9:0] 3ff r/w fp_proximity_recal full power mode proximity recalibration time control [15:10] 3f lp_proximity_recal low power mode proximity recalibration time control
AD7143 rev. 0 | page 38 of 56 table 21. stage_low_int_en register address data bit default type name description [0] 0 stage0_low_int_en stage0 low interrupt enable 0 = interrupt source disabled 1 = int asserted if stage0 low threshold is exceeded [1] 0 stage1_low_int_en stage1 low interrupt enable 0 = interrupt source disabled 1 = int asserted if stage0 low threshold is exceeded [2] 0 stage2_low_int_en stage2 low interrupt enable 0 = interrupt source disabled 1 = int asserted if stage0 low threshold is exceeded [3] 0 stage3_low_int_en stage3 low interrupt enable 0 = interrupt source disabled 1 = int asserted if stage0 low threshold is exceeded [4] 0 stage4_low_int_en stage4 low interrupt enable 0 = interrupt source disabled 1 = int asserted if stage0 low threshold is exceeded 0x005 [5] 0 stage5_low_int_en stage5 low interrupt enable 0 = interrupt source disabled 1 = int asserted if stage0 low threshold is exceeded r/w [6] 0 stage6_low_int_en stage6 low interrupt enable 0 = interrupt source disabled 1 = int asserted if stage0 low threshold is exceeded [7] 0 stage7_low_int_en stage7 low interrupt enable 0 = interrupt source disabled 1 = int asserted if stage0 low threshold is exceeded [11:8] 0 unused set unused register bits = 0 [15:12] 0 testmode set test mode register bits = 0 (at all times)
AD7143 rev. 0 | page 39 of 56 table 22. stage_high_int_en register address data bit default type name description [0] 0 stage0_high_int_en stage0 high interrupt enable 0 = interrupt source disabled 1 = int asserted if stage0 high threshold is exceeded [1] 0 stage1_high_int_en stage1 high interrupt enable 0 = interrupt source disabled 1 = int asserted if stage0 high threshold is exceeded [2] 0 stage2_high_int_en stage2 high interrupt enable 0 = interrupt source disabled 1 = int asserted if stage0 high threshold is exceeded [3] 0 stage3_high_int_en stage3 high interrupt enable 0 = interrupt source disabled 1 = int asserted if stage0 high threshold is exceeded [4] 0 stage4_high_int_en stage4 high interrupt enable 0 = interrupt source disabled 1 = int asserted if stage0 high threshold is exceeded [5] 0 stage5_high_int_en stage5 high interrupt enable 0 = interrupt source disabled 1 = int asserted if stage0 high threshold is exceeded [6] 0 stage6_high_int_en stage6 high interrupt enable 0 = interrupt source disabled 1 = int asserted if stage0 high threshold is exceeded [7] 0 stage7_high_int_en stage7 high interrupt enable 0 = interrupt source disabled 1 = int asserted if stage0 high threshold is exceeded 0x006 [15:8] r/w unused set unused register bits = 0
AD7143 rev. 0 | page 40 of 56 table 23. stage_complete_int_en register address data bit default type name description 0x007 [0] 0 r/w stage0_complete_en stage0 conversion interrupt control 0 = interrupt source disabled 1 = int asserted at completion of stage0 conversion [1] 0 stage1_complete_en stage1 conversion interrupt control 0 = interrupt source disabled 1 = int asserted at completion of stage1 conversion [2] 0 stage2_complete_en stage2 conversion interrupt control 0 = interrupt source disabled 1 = int asserted at completion of stage2 conversion [3] 0 stage3_complete_en stage3 conversion interrupt control 0 = interrupt source disabled 1 = int asserted at completion of stage3 conversion [4] 0 stage4_complete_en stage4 conversion interrupt control 0 = interrupt source disabled 1 = int asserted at completion of stage4 conversion [5] 0 stage5_complete_en stage5 conversion interrupt control 0 = interrupt source disabled 1 = int asserted at completion of stage5 conversion [6] 0 stage6_complete_en stage6 conversion interrupt control 0 = interrupt source disabled 1 = int asserted at completion of stage6 conversion [7] 0 stage7_complete_en stage7 conversion interrupt control 0 = interrupt source disabled 1 = int asserted at completion of stage7 conversion [11:8] 0 unused set unused register bits = 0 [12] 0 testmode set test mode register bits = 0 at all times [15:13] unused set unused register bits = 0 table 24. stage_low_limit_int register 1 address data bit default type name description 0x008 [0] 0 r stage0_low_limit_int stage0 cdc conversion low limit interrupt result 1 indicates stage0_low_threshold value exceeded [1] 0 stage1_low_limit_int stage1 cdc conversion low limit interrupt result 1 indicates stage1_low_threshold value exceeded [2] 0 stage2_low_limit_int stage2 cdc conversion low limit interrupt result 1 indicates stage2_low_threshold value exceeded [3] 0 stage3_low_limit_int stage3 cdc conversion low limit interrupt result 1 indicates stage3_low_threshold value exceeded [4] 0 stage4_low_limit_int stage4 cdc conversion low limit interrupt result 1 indicates stage4_low_threshold value exceeded [5] 0 stage5_low_limit_int stage5 cdc conversion low limit interrupt result 1 indicates stage5_low_threshold value exceeded [6] 0 stage6_low_limit_int stage6 cdc conversion low limit interrupt result 1 indicates stage6_low_threshold value exceeded [7] 0 stage7_low_limit_int stage7 cdc conversion low limit interrupt result 1 indicates stage7_low_threshold value exceeded [15:8] unused set unused register bits = 0 1 registers self-clear to 0 af ter readback, provided that the limits are not exceeded.
AD7143 rev. 0 | page 41 of 56 table 25. stage_high_limit_int register 1 address data bit default type name description 0x009 [0] 0 r stage0_high_limit_int stage0 cdc conversion high limit interrupt result 1 indicates stage0_high_threshold value exceeded [1] 0 stage1_high_limit_int stage1 cdc conversion high limit interrupt result 1 indicates stage1_high_threshold value exceeded [2] 0 stage2_high_limit_int stage2 cdc conversion high limit interrupt result 1 indicates stage2_high_threshold value exceeded [3] 0 stage3_high_limit_int stage3 cdc conversion high limit interrupt result 1 indicates stage3_high_threshold value exceeded [4] 0 stage4_high_limit_int stage4 cdc conversion high limit interrupt result 1 indicates stage4_high_threshold value exceeded [5] 0 stage5_high_limit_int stage5 cdc conversion high limit interrupt result 1 indicates stage5_high_threshold value exceeded [6] 0 stage6_high_limit_int stage6 cdc conversion high limit interrupt result 1 indicates stage6_high_threshold value exceeded [7] 0 stage7_high_limit_int stage7 cdc conversion high limit interrupt result 1 indicates stage7_high_threshold value exceeded [15:8] unused set unused register bits = 0 1 registers self-clear to 0 af ter readback, provided that the limits are not exceeded. table 26. stage_complete_limit_int register 1 address data bit default type name description 0x00a [0] 0 r stage0_complete_status_int stage0 conversion complete register interrupt status 1 indicates stage0 conversion completed [1] 0 stage1_complete_status_int stage1 conversion complete register interrupt status 1 indicates stage0 conversion completed [2] 0 stage2_complete_status_int stage2 conversion complete register interrupt status 1 indicates stage0 conversion completed [3] 0 stage3_complete_status_int stage3 conversion complete register interrupt status 1 indicates stage0 conversion completed [4] 0 stage4_complete_status_int stage4 conversion complete register interrupt status 1 indicates stage0 conversion completed [5] 0 stage5_complete_status_int stage5 conversion complete register interrupt status 1 indicates stage0 conversion completed [6] 0 stage6_complete_status_int stage6 conversion complete register interrupt status 1 indicates stage0 conversion completed [7] 0 stage7_complete_status_int stage7 conversion complete register interrupt status 1 indicates stage0 conversion completed [15:8] 0 unused 1 registers self-clear to 0 after readback, provided that the limits are not exceeded.
AD7143 rev. 0 | page 42 of 56 table 27. cdc 16-bit conversion data registers address data bit default type name description 0x00b [15:0] 0 r adc_result_s0 stage0 cdc 16-bit conversion data 0x00c [15:0] 0 r adc_result_s1 stage1 cdc 16-bit conversion data 0x00d [15:0] 0 r adc_result_s2 stage2 cdc 16-bit conversion data 0x00e [15:0] 0 r adc_result_s3 stage3 cdc 16-bit conversion data 0x00f [15:0] 0 r adc_result_s4 stage4 cdc 16-bit conversion data 0x010 [15:0] 0 r adc_result_s5 stage5 cdc 16-bit conversion data 0x011 [15:0] 0 r adc_result_s6 stage6 cdc 16-bit conversion data 0x012 [15:0] 0 r adc_result_s7 stage7 cdc 16-bit conversion data table 28. device id register address data bit default type name description 0x017 [3:0] 0 r revision_code AD7143 revision code [15:4] e63 devid AD7143 device id = 0xe63 table 29. proximity status register address data bit default type name description 0x042 [0] 0 r stage0_proximity_status stage0 proximity status register 1 indicates proximity detected on stage0 [1] 0 r stage1_proximity_status stage1 proximity status register 1 indicates proximity detected on stage1 [2] 0 r stage2_proximity_status stage2 proximity status register 1 indicates proximity detected on stage2 [3] 0 r stage3_proximity_status stage3 proximity status register 1 indicates proximity detected on stage3 [4] 0 r stage4_proximity_status stage4 proximity status register 1 indicates proximity detected on stage4 [5] 0 r stage5_proximity_status stage5 proximity status register 1 indicates proximity detected on stage5 [6] 0 r stage6_proximity_status stage6 proximity status register 1 indicates proximity detected on stage6 [7] 0 r stage7_proximity_status stage7 proximity status register 1 indicates proximity detected on stage7 [15:8] unused set unused register bits = 0
AD7143 rev. 0 | page 43 of 56 bank 2 registers all address values are expressed in hexadecimal format. table 30. stage0 configuration registers address data bit default type name description 0x080 [15:0] x r/w stage0_connection[6:0] stage0 cin(6:0) connection setup (see table 38 ) 0x081 [15:0] x r/w stage0_connection 7 stage0 cin7 connection setup (see table 39 ) 0x082 [15:0] x r/w stage0_afe_offset stage0 afe offset control (see table 40 ) 0x083 [15:0] x r/w stage0_sensitivity stage0 sensitivity control (see table 41 ) 0x084 [15:0] x r/w stage0_offset_low stage0 initial offset low value 0x085 [15:0] x r/w stage0_offset_high stage0 initial offset high value 0x086 [15:0] x r/w stage0_offset_high_clamp stage0 offset high clamp value 0x087 [15:0] x r/w stage0_offset_low_clamp stage0 offset low clamp value table 31. stage1 configuration registers address data bit default type name description 0x088 [15:0] x r/w stage1_connection[6:0] stage1 cin(6:0) connection setup (see table 38 ) 0x089 [15:0] x r/w stage1_connection 7 stage1 cin7 connection setup (see table 39 ) 0x08a [15:0] x r/w stage1_afe_offset stage1 afe offset control (see table 40 ) 0x08b [15:0] x r/w stage1_sensitivity stage1 sensitivity control (see table 41 ) 0x08c [15:0] x r/w stage1_offset_low stage1 initial offset low value 0x08d [15:0] x r/w stage1_offset_high stage1 initial offset high value 0x08e [15:0] x r/w stage1_offset_high_clamp stage1 offset high clamp value 0x08f [15:0] x r/w stage1_offset_low_clamp stage1 offset low clamp value table 32. stage2 configuration registers address data bit default type name description 0x090 [15:0] x r/w stage2_connection[6:0] stage2 cin(6:0) connection setup (see table 38 ) 0x091 [15:0] x r/w stage2_connection 7 stage2 cin7 connection setup (see table 39 ) 0x092 [15:0] x r/w stage2_afe_offset stage2 afe offset control (see table 40 ) 0x093 [15:0] x r/w stage2_sensitivity stage2 sensitivity control (see table 41 ) 0x094 [15:0] x r/w stage2_offset_low stage2 initial offset low value 0x095 [15:0] x r/w stage2_offset_high stage2 initial offset high value 0x096 [15:0] x r/w stage2_offset_high_clamp stage2 offset high clamp value 0x097 [15:0] x r/w stage2_offset_low_clamp stage2 offset low clamp value
AD7143 rev. 0 | page 44 of 56 table 33. stage3 configuration registers address data bit default type name description 0x098 [15:0] x r/w stage3_connection[6:0] stage3 cin(6:0) connection setup (see table 38 ) 0x099 [15:0] x r/w stage3_connection 7 stage3 cin7 connection setup (see table 39 ) 0x09a [15:0] x r/w stage3_afe_offset stage3 afe offset control (see table 40 ) 0x09b [15:0] x r/w stage3_sensitivity stage3 sensitivity control (see table 41 ) 0x09c [15:0] x r/w stage3_offset_low stage3 initial offset low value 0x09d [15:0] x r/w stage3_offset_high stage3 initial offset high value 0x09e [15:0] x r/w stage3_offset_high_clamp stage3 offset high clamp value 0x09f [15:0] x r/w stage3_offset_low_clamp stage3 offset low clamp value table 34. stage4 configuration registers address data bit default type name description 0x0a0 [15:0] x r/w stage4_connection[6: 0] stage4 cin(6:0) connection setup (see table 38 ) 0x0a1 [15:0] x r/w stage4_connectio n 7 stage4 cin7 connection setup (see table 39 ) 0x0a2 [15:0] x r/w stage4_afe_offset stage4 afe offset control (see table 40 ) 0x0a3 [15:0] x r/w stage4_sensitivity stage4 sensitivity control (see table 41 ) 0x0a4 [15:0] x r/w stage4_offset_low stage4 initial offset low value 0x0a5 [15:0] x r/w stage4_offset_high stage4 initial offset high value 0x0a6 [15:0] x r/w stage4_offset_high_clamp stage4 offset high clamp value 0x0a7 [15:0] x r/w stage4_offset_low_clamp stage4 offset low clamp value table 35. stage5 configuration registers address data bit default type name description 0x0a8 [15:0] x r/w stage5_connection[6: 0] stage5 cin(6:0) connection setup (see table 38 ) 0x0a9 [15:0] x r/w stage5_connectio n 7 stage5 cin7 connection setup (see table 39 ) 0x0aa [15:0] x r/w stage5_afe_offset stage5 afe offset control (see table 40 ) 0x0ab [15:0] x r/w stage5_sensitivity stage5 sensitivity control (see table 41 ) 0x0ac [15:0] x r/w stage5_offset_low stage5 initial offset low value 0x0ad [15:0] x r/w stage5_offset_high stage5 initial offset high value 0x0ae [15:0] x r/w stage5_offset_high_clamp stage5 offset high clamp value 0x0af [15:0] x r/w stage5_offset_low_clamp stage5 offset low clamp value table 36. stage6 configuration registers address data bit default type name description 0x0b0 [15:0] x r/w stage6_connection[6: 0] stage6 cin(6:0) connection setup (see table 38 ) 0x0b1 [15:0] x r/w stage6_connectio n 7 stage6 cin7 connection setup (see table 39 ) 0x0b2 [15:0] x r/w stage6_afe_offset stage6 afe offset control (see table 40 ) 0x0b3 [15:0] x r/w stage6_sensitivity stage6 sensitivity control (see table 41 ) 0x0b4 [15:0] x r/w stage6_offset_low stage6 initial offset low value 0x0b5 [15:0] x r/w stage6_offset_high stage6 initial offset high value 0x0b6 [15:0] x r/w stage6_offset_high_clamp stage6 offset high clamp value 0x0b7 [15:0] x r/w stage6_offset_low_clamp stage6 offset low clamp value
AD7143 rev. 0 | page 45 of 56 table 37. stage7 configuration registers address data bit default type name description 0x0b8 [15:0] x r/w stage7_connection[6: 0] stage7 cin(6:0) connection setup (see table 38 ) 0x0b9 [15:0] x r/w stage7_connectio n 7 stage7 cin7 connection setup (see table 39 ) 0x0ba [15:0] x r/w stage7_afe_offset stage7 afe offset control (see table 40 ) 0x0bb [15:0] x r/w stage7_sensitivity stage7 sensitivity control (see table 41 ) 0x0bc [15:0] x r/w stage7_offset_low stage7 initial offset low value 0x0bd [15:0] x r/w stage7_offset_high stage7 initial offset high value 0x0be [15:0] x r/w stage7_offset_high_clamp stage7 offset high clamp value 0x0bf [15:0] x r/w stage7_offset_low_clamp stage7 offset low clamp value table 38. stagex detailed cin (0:6) connection setup description (x = 0 to 6) data bit default type name description [1:0] x r/w cin0_connection_setup cin0 connection setup 00 = cin0 not connected to cdc inputs 01 = cin0 connected to cdc negative input 10 = cin0 connected to cdc positive input 11 = cin0 connected to bias (connect unused cin inputs) [3:2] x r/w cin1_connection_setup cin1 connection setup 00 = cin1 not connected to cdc inputs 01 = cin1 connected to cdc negative input 10 = cin1 connected to cdc positive input 11 = cin1 connected to bias (connect unused cin inputs) [5:4] x r/w cin2_connection_setup cin2 connection setup 00 = cin2 not connected to cdc inputs 01 = cin2 connected to cdc negative input 10 = cin2 connected to cdc positive input 11 = cin2 connected to bias (connect unused cin inputs) [7:6] x r/w cin3_connection_setup cin3 connection setup 00 = cin3 not connected to cdc inputs 01 = cin3 connected to cdc negative input 10 = cin3 connected to cdc positive input 11 = cin3 connected to bias (connect unused cin inputs) [9:8] x r/w cin4_connection_setup cin4 connection setup 00 = cin4 not connected to cdc inputs 01 = cin4 connected to cdc negative input 10 = cin4 connected to cdc positive input 11 = cin4 connected to bias (connect unused cin inputs) [11:10] x r/w cin5_connection_setup cin5 connection setup 00 = cin5 not connected to cdc inputs 01 = cin5 connected to cdc negative input 10 = cin5 connected to cdc positive input 11 = cin5 connected to bias (connect unused cin inputs) [13:12] x r/w cin6_connection_setup cin6 connection setup 00 = cin6 not connected to cdc inputs 01 = cin6 connected to cdc negative input 10 = cin6 connected to cdc positive input 11 = cin6 connected to bias (connect unused cin inputs) [15:14] x unused
AD7143 rev. 0 | page 46 of 56 table 39. stagex detailed cin7 connection setup description data bit default type name description [1:0] x r/w cin7_connection_setup cin7 connection setup 00 = cin7 not connected to cdc inputs 01 = cin7 connected to cdc negative input 10 = cin7 connected to cdc positive input 11 = cin7 connected to bias (connect unused cin inputs) [13:2] x r/w unused [14] x r/w neg_afe_offset_disable negative afe offset enable control 0 = enable 1 = disable [15] x r/w pos_afe_offset_disable positive afe offset enable control 0 = enable 1 = disable table 40. stagex detailed offset control description (x = 0 to 7) data bit default type name description [6:0] x r/w neg_afe_offset negative afe offset setting (20 pf range) 1 lsb value = 0.16 pf of offset [7] x r/w neg_afe_offset_swap negative afe offset swap control 0 = neg_afe_offset applied to cdc negative input 1 = neg_afe_offset applied to cdc positive input [14:8] x r/w pos_afe_offset positive afe offset setting (20 pf range) 1 lsb value = 0.16 pf of offset [15] x r/w pos_afe_offset_swap positive afe offset swap control 0 = pos_afe_offset applied to cdc positive input 1 = pos_afe_offset applied to cdc negative input table 41. stagex detailed sensitivity control description (x = 0 to 7) data bit default type name description [3:0] x r/w neg_threshold_sensitivity negative threshold sensitivity control 0000 = 25%, 0001 = 29.73%, 0010 = 34.40%, 0011 = 39.08% 0100 = 43.79%, 0101 = 48.47%, 0110 = 53.15% 0111 = 57.83%, 1000 = 62.51%, 1001 = 67.22% 1010 = 71.90%, 1011 = 76.58%, 1100 = 81.28% 1101 = 85.96%, 1110 = 90.64%, 1111 = 95.32% [6:4] x r/w neg_peak_detect ne gative peak detect setting 000 = 40% level, 001 = 50% level, 010 = 60% level 011 = 70% level, 100 = 80% level, 101 = 90% level [7] x r/w unused [11:8] x r/w pos_threshold_sensitivity positive threshold sensitivity control 0000 = 25%, 0001 = 29.73%, 0010 = 34.40%, 0011 = 39.08% 0100 = 43.79%, 0101 = 48.47%, 0110 = 53.15% 0111 = 57.83%, 1000 = 62.51%, 1001 = 67.22% 1010 = 71.90%, 1011 = 76.58%, 1100 = 81.28% 1101 = 85.96%, 1110 = 90.64%, 1111 = 95.32% [14:12] x r/w pos_peak_detect positive peak detect setting 000 = 40% level, 001 = 50% level, 010 = 60% level 011 = 70% level, 100 = 80% level, 101 = 90% level [15] x r/w unused
AD7143 rev. 0 | page 47 of 56 bank 3 registers all address values are expressed in hexadecimal format. table 42. stage0 results registers address data bit default type name description 0x0e0 [15:0] x r/w stage0_conv_data stage0 cdc 16-bit conversion data (copy of data in stage0_conv_data register) 0x0e1 [15:0] x r/w stage0_ff_word0 stage0 fast fifo word0 0x0e2 [15:0] x r/w stage0_ff_word1 stage0 fast fifo word1 0x0e3 [15:0] x r/w stage0_ff_word2 stage0 fast fifo word2 0x0e4 [15:0] x r/w stage0_ff_word3 stage0 fast fifo word3 0x0e5 [15:0] x r/w stage0_ff_word4 stage0 fast fifo word4 0x0e6 [15:0] x r/w stage0_ff_word5 stage0 fast fifo word5 0x0e7 [15:0] x r/w stage0_ff_word6 stage0 fast fifo word6 0x0e8 [15:0] x r/w stage0_ff_word7 stage0 fast fifo word7 0x0e9 [15:0] x r/w stage0_sf_word0 stage0 slow fifo word0 0x0ea [15:0] x r/w stage0_sf_word1 stage0 slow fifo word1 0x0eb [15:0] x r/w stage0_sf_word2 stage0 slow fifo word2 0x0ec [15:0] x r/w stage0_sf_word3 stage0 slow fifo word3 0x0ed [15:0] x r/w stage0_sf_word4 stage0 slow fifo word4 0x0ee [15:0] x r/w stage0_sf_word5 stage0 slow fifo word5 0x0ef [15:0] x r/w stage0_sf_word6 stage0 slow fifo word6 0x0f0 [15:0] x r/w stage0_sf_word7 stage0 slow fifo word7 0x0f1 [15:0] x r/w stage0_sf_ambient stage0 slow fifo ambient value 0x0f2 [15:0] x r/w stage0_ff_avg stage0 fast fifo average value 0x0f3 [15:0] x r/w stage0_peak_detect_ word0 stage0 peak fifo word0 value 0x0f4 [15:0] x r/w stage0_peak_detect_ word1 stage0 peak fifo word1 value 0x0f5 [15:0] x r/w stage0_max_word0 stage0 maximum value fifo word0 0x0f6 [15:0] x r/w stage0_max_word1 stage0 maximum value fifo word1 0x0f7 [15:0] x r/w stage0_max_word2 stage0 maximum value fifo word2 0x0f8 [15:0] x r/w stage0_max_word3 stage0 maximum value fifo word3 0x0f9 [15:0] x r/w stage0_max_avg stage0 average maximum fifo value 0x0fa [15:0] x r/w stage0_high_threshold stage0 high threshold value 0x0fb [15:0] x r/w stage0_max_temp stage0 temporary maximum value 0x0fc [15:0] x r/w stage0_min_word0 stage0 minimum value fifo word0 0x0fd [15:0] x r/w stage0_min_word1 stage0 minimum value fifo word1 0x0fe [15:0] x r/w stage0_min_word2 stage0 minimum value fifo word2 0x0ff [15:0] x r/w stage0_min_word3 stage0 minimum value fifo word3 0x100 [15:0] x r/w stage0_min_avg stage0 average minimum fifo value 0x101 [15:0] x r/w stage0_low_thres hold stage0 low threshold value 0x102 [15:0] x r/w stage0_min_temp stage0 temporary minimum value 0x103 [15:0] x r/w unused
AD7143 rev. 0 | page 48 of 56 table 43. stage1 results registers address data bit default type name description 0x104 [15:0] x r/w stage1_conv_data stage1 cdc 16-bit conversion data (copy of data in stage1_conv_data register) 0x105 [15:0] x r/w stage1_ff_word0 stage1 fast fifo word0 0x106 [15:0] x r/w stage1_ff_word1 stage1 fast fifo word1 0x107 [15:0] x r/w stage1_ff_word2 stage1 fast fifo word2 0x108 [15:0] x r/w stage1_ff_word3 stage1 fast fifo word3 0x109 [15:0] x r/w stage1_ff_word4 stage1 fast fifo word4 0x10a [15:0] x r/w stage1_ff_word5 stage1 fast fifo word5 0x10b [15:0] x r/w stage1_ff_word6 stage1 fast fifo word6 0x10c [15:0] x r/w stage1_ff_word7 stage1 fast fifo word7 0x10d [15:0] x r/w stage1_sf_word0 stage1 slow fifo word0 0x10e [15:0] x r/w stage1_sf_word1 stage1 slow fifo word1 0x10f [15:0] x r/w stage1_sf_word2 stage1 slow fifo word2 0x110 [15:0] x r/w stage1_sf_word3 stage1 slow fifo word3 0x111 [15:0] x r/w stage1_sf_word4 stage1 slow fifo word4 0x112 [15:0] x r/w stage1_sf_word5 stage1 slow fifo word5 0x113 [15:0] x r/w stage1_sf_word6 stage1 slow fifo word6 0x114 [15:0] x r/w stage1_sf_word7 stage1 slow fifo word7 0x115 [15:0] x r/w stage1_sf_ambient stage1 slow fifo ambient value 0x116 [15:0] x r/w stage1_ff_avg stage1 fast fifo average value 0x117 [15:0] x r/w stage1_cdc_word0 stage1 cdc fifo word0 0x118 [15:0] x r/w stage1_cdc_word1 stage1 cdc fifo word1 0x119 [15:0] x r/w stage1_max_word0 stage1 maximum value fifo word0 0x11a [15:0] x r/w stage1_max_word1 stage1 maximum value fifo word1 0x11b [15:0] x r/w stage1_max_word2 stage1 maximum value fifo word2 0x11c [15:0] x r/w stage1_max_word3 stage1 maximum value fifo word3 0x11d [15:0] x r/w stage1_max_avg stage1 average maximum fifo value 0x11e [15:0] x r/w stage1_high_threshold stage1 high threshold value 0x11f [15:0] x r/w stage1_max_temp stage1 temporary maximum value 0x120 [15:0] x r/w stage1_min_word0 stage1 minimum value fifo word0 0x121 [15:0] x r/w stage1_min_word1 stage1 minimum value fifo word1 0x122 [15:0] x r/w stage1_min_word2 stage1 minimum value fifo word2 0x123 [15:0] x r/w stage1_min_word3 stage1 minimum value fifo word3 0x124 [15:0] x r/w stage1_min_avg stage1 average minimum fifo value 0x125 [15:0] x r/w stage1_low_thres hold stage1 low threshold value 0x126 [15:0] x r/w stage1_min_temp stage1 temporary minimum value 0x127 [15:0] x r/w unused
AD7143 rev. 0 | page 49 of 56 table 44. stage2 results registers address data bit default type name description 0x128 [15:0] x r/w stage2_conv_data stage2 cdc 16-bit conversion data (copy of data in stage2_conv_data register) 0x129 [15:0] x r/w stage2_ff_word0 stage2 fast fifo word0 0x12a [15:0] x r/w stage2_ff_word1 stage2 fast fifo word1 0x12b [15:0] x r/w stage2_ff_word2 stage2 fast fifo word2 0x12c [15:0] x r/w stage2_ff_word3 stage2 fast fifo word3 0x12d [15:0] x r/w stage2_ff_word4 stage2 fast fifo word4 0x12e [15:0] x r/w stage2_ff_word5 stage2 fast fifo word5 0x12f [15:0] x r/w stage2_ff_word6 stage2 fast fifo word6 0x130 [15:0] x r/w stage2_ff_word7 stage2 fast fifo word7 0x131 [15:0] x r/w stage2_sf_word0 stage2 slow fifo word0 0x132 [15:0] x r/w stage2_sf_word1 stage2 slow fifo word1 0x133 [15:0] x r/w stage2_sf_word2 stage2 slow fifo word2 0x134 [15:0] x r/w stage2_sf_word3 stage2 slow fifo word3 0x135 [15:0] x r/w stage2_sf_word4 stage2 slow fifo word4 0x125 [15:0] x r/w stage2_sf_word5 stage2 slow fifo word5 0x137 [15:0] x r/w stage2_sf_word6 stage2 slow fifo word6 0x138 [15:0] x r/w stage2_sf_word7 stage2 slow fifo word7 0x139 [15:0] x r/w stage2_sf_ambient stage2 slow fifo ambient value 0x13a [15:0] x r/w stage2_ff_avg stage2 fast fifo average value 0x13b [15:0] x r/w stage2_cdc_word0 stage2 cdc fifo word0 0x13c [15:0] x r/w stage2_cdc_word1 stage2 cdc fifo word1 0x13d [15:0] x r/w stage2_max_word0 stage2 maximum value fifo word0 0x13e [15:0] x r/w stage2_max_word1 stage2 maximum value fifo word1 0x13f [15:0] x r/w stage2_max_word2 stage2 maximum value fifo word2 0x140 [15:0] x r/w stage2_max_word3 stage2 maximum value fifo word3 0x141 [15:0] x r/w stage2_max_avg stage2 average maximum fifo value 0x142 [15:0] x r/w stage2_high_threshold stage2 high threshold value 0x143 [15:0] x r/w stage2_max_temp stage2 temporary maximum value 0x144 [15:0] x r/w stage2_min_word0 stage2 minimum value fifo word0 0x145 [15:0] x r/w stage2_min_word1 stage2 minimum value fifo word1 0x146 [15:0] x r/w stage2_min_word2 stage2 minimum value fifo word2 0x147 [15:0] x r/w stage2_min_word3 stage2 minimum value fifo word3 0x148 [15:0] x r/w stage2_min_avg stage2 average minimum fifo value 0x149 [15:0] x r/w stage2_low_thres hold stage2 low threshold value 0x14a [15:0] x r/w stage2_min_temp stage2 temporary minimum value 0x14b [15:0] x r/w unused
AD7143 rev. 0 | page 50 of 56 table 45. stage3 results registers address data bit default type name description 0x14c [15:0] x r/w stage3_conv_data stage3 cdc 16-bit conversion data (copy of data in stage3_conv_data register) 0x14d [15:0] x r/w stage3_ff_word0 stage3 fast fifo word0 0x14e [15:0] x r/w stage3_ff_word1 stage3 fast fifo word1 0x14f [15:0] x r/w stage3_ff_word2 stage3 fast fifo word2 0x150 [15:0] x r/w stage3_ff_word3 stage3 fast fifo word3 0x151 [15:0] x r/w stage3_ff_word4 stage3 fast fifo word4 0x152 [15:0] x r/w stage3_ff_word5 stage3 fast fifo word5 0x153 [15:0] x r/w stage3_ff_word6 stage3 fast fifo word6 0x154 [15:0] x r/w stage3_ff_word7 stage3 fast fifo word7 0x155 [15:0] x r/w stage3_sf_word0 stage3 slow fifo word0 0x156 [15:0] x r/w stage3_sf_word1 stage3 slow fifo word1 0x157 [15:0] x r/w stage3_sf_word2 stage3 slow fifo word2 0x158 [15:0] x r/w stage3_sf_word3 stage3 slow fifo word3 0x159 [15:0] x r/w stage3_sf_word4 stage3 slow fifo word4 0x15a [15:0] x r/w stage3_sf_word5 stage3 slow fifo word5 0x15b [15:0] x r/w stage3_sf_word6 stage3 slow fifo word6 0x15c [15:0] x r/w stage3_sf_word7 stage3 slow fifo word7 0x15d [15:0] x r/w stage3_sf_ambient stage3 slow fifo ambient value 0x15e [15:0] x r/w stage3_ff_avg stage3 fast fifo average value 0x15f [15:0] x r/w stage3_cdc_word0 stage3 cdc fifo word0 0x160 [15:0] x r/w stage3_cdc_word1 stage3 cdc fifo word1 0x161 [15:0] x r/w stage3_max_word0 stage3 maximum value fifo word0 0x162 [15:0] x r/w stage3_max_word1 stage3 maximum value fifo word1 0x163 [15:0] x r/w stage3_max_word2 stage3 maximum value fifo word2 0x164 [15:0] x r/w stage3_max_word3 stage3 maximum value fifo word3 0x165 [15:0] x r/w stage3_max_avg stage3 average maximum fifo value 0x166 [15:0] x r/w stage3_high_threshold stage3 high threshold value 0x167 [15:0] x r/w stage3_max_temp stage3 temporary maximum value 0x168 [15:0] x r/w stage3_min_word0 stage3 minimum value fifo word0 0x169 [15:0] x r/w stage3_min_word1 stage3 minimum value fifo word1 0x16a [15:0] x r/w stage3_min_word2 stage3 minimum value fifo word2 0x16b [15:0] x r/w stage3_min_word3 stage3 minimum value fifo word3 0x16c [15:0] x r/w stage3_min_avg stage3 average minimum fifo value 0x16d [15:0] x r/w stage3_low_thr eshold stage3 low threshold value 0x16e [15:0] x r/w stage3_min_temp stage3 temporary minimum value 0x16f [15:0] x r/w unused
AD7143 rev. 0 | page 51 of 56 table 46. stage4 results registers address data bit default type name description 0x170 [15:0] x r/w stage4_conv_data stage4 cdc 16-bit conversion data (copy of data in stage4_conv_data register) 0x171 [15:0] x r/w stage4_ff_word0 stage4 fast fifo word0 0x172 [15:0] x r/w stage4_ff_word1 stage4 fast fifo word1 0x173 [15:0] x r/w stage4_ff_word2 stage4 fast fifo word2 0x174 [15:0] x r/w stage4_ff_word3 stage4 fast fifo word3 0x175 [15:0] x r/w stage4_ff_word4 stage4 fast fifo word4 0x176 [15:0] x r/w stage4_ff_word5 stage4 fast fifo word5 0x177 [15:0] x r/w stage4_ff_word6 stage4 fast fifo word6 0x178 [15:0] x r/w stage4_ff_word7 stage4 fast fifo word7 0x179 [15:0] x r/w stage4_sf_word0 stage4 slow fifo word0 0x17a [15:0] x r/w stage4_sf_word1 stage4 slow fifo word1 0x17b [15:0] x r/w stage4_sf_word2 stage4 slow fifo word2 0x17c [15:0] x r/w stage4_sf_word3 stage4 slow fifo word3 0x17d [15:0] x r/w stage4_sf_word4 stage4 slow fifo word4 0x17e [15:0] x r/w stage4_sf_word5 stage4 slow fifo word5 0x17f [15:0] x r/w stage4_sf_word6 stage4 slow fifo word6 0x180 [15:0] x r/w stage4_sf_word7 stage4 slow fifo word7 0x181 [15:0] x r/w stage4_sf_ambient stage4 slow fifo ambient value 0x182 [15:0] x r/w stage4_ff_avg stage4 fast fifo average value 0x183 [15:0] x r/w stage4_cdc_word0 stage4 cdc fifo word0 0x184 [15:0] x r/w stage4_cdc_word1 stage4 cdc fifo word1 0x185 [15:0] x r/w stage4_max_word0 stage4 maximum value fifo word0 0x186 [15:0] x r/w stage4_max_word1 stage4 maximum value fifo word1 0x187 [15:0] x r/w stage4_max_word2 stage4 maximum value fifo word2 0x188 [15:0] x r/w stage4_max_word3 stage4 maximum value fifo word3 0x189 [15:0] x r/w stage4_max_avg stage4 average maximum fifo value 0x18a [15:0] x r/w stage4_high_threshold stage4 high threshold value 0x18b [15:0] x r/w stage4_max_temp stage4 temporary maximum value 0x18c [15:0] x r/w stage4_min_word0 stage4 minimum value fifo word0 0x18d [15:0] x r/w stage4_min_word1 stage4 minimum value fifo word1 0x18e [15:0] x r/w stage4_min_word2 stage4 minimum value fifo word2 0x18f [15:0] x r/w stage4_min_word3 stage4 minimum value fifo word3 0x190 [15:0] x r/w stage4_min_avg stage4 average minimum fifo value 0x191 [15:0] x r/w stage4_low_thres hold stage4 low threshold value 0x192 [15:0] x r/w stage4_min_temp stage4 temporary minimum value 0x193 [15:0] x r/w unused
AD7143 rev. 0 | page 52 of 56 table 47. stage5 results registers address data bit default type name description 0x194 [15:0] x r/w stage5_conv_data stage5 cdc 16-bit conversion data (copy of data in stage5_conv_data register) 0x195 [15:0] x r/w stage5_ff_word0 stage5 fast fifo word0 0x196 [15:0] x r/w stage5_ff_word1 stage5 fast fifo word1 0x197 [15:0] x r/w stage5_ff_word2 stage5 fast fifo word2 0x198 [15:0] x r/w stage5_ff_word3 stage5 fast fifo word3 0x199 [15:0] x r/w stage5_ff_word4 stage5 fast fifo word4 0x19a [15:0] x r/w stage5_ff_word5 stage5 fast fifo word5 0x19b [15:0] x r/w stage5_ff_word6 stage5 fast fifo word6 0x19c [15:0] x r/w stage5_ff_word7 stage5 fast fifo word7 0x19d [15:0] x r/w stage5_sf_word0 stage5 slow fifo word0 0x19e [15:0] x r/w stage5_sf_word1 stage5 slow fifo word1 0x19f [15:0] x r/w stage5_sf_word2 stage5 slow fifo word2 0x1a0 [15:0] x r/w stage5_sf_word3 stage5 slow fifo word3 0x1a1 [15:0] x r/w stage5_sf_word4 stage5 slow fifo word4 0x1a2 [15:0] x r/w stage5_sf_word5 stage5 slow fifo word5 0x1a3 [15:0] x r/w stage5_sf_word6 stage5 slow fifo word6 0x1a4 [15:0] x r/w stage5_sf_word7 stage5 slow fifo word7 0x1a5 [15:0] x r/w stage5_sf_ambient stage5 slow fifo ambient value 0x1a6 [15:0] x r/w stage5_ff_avg stage5 fast fifo average value 0x1a7 [15:0] x r/w stage5_cdc_word0 stage5 cdc fifo word0 0x1a8 [15:0] x r/w stage5_cdc_word1 stage5 cdc fifo word1 0x1a9 [15:0] x r/w stage5_max_word0 stage5 maximum value fifo word0 0x1aa [15:0] x r/w stage5_max_word1 stage5 maximum value fifo word1 0x1ab [15:0] x r/w stage5_max_word2 stage5 maximum value fifo word2 0x1ac [15:0] x r/w stage5_max_word3 stage5 maximum value fifo word3 0x1ad [15:0] x r/w stage5_max_avg stage5 average maximum fifo value 0x1ae [15:0] x r/w stage5_high_thre shold stage5 high threshold value 0x1af [15:0] x r/w stage5_max_temp stage5 temporary maximum value 0x1b0 [15:0] x r/w stage5_min_word0 stage5 minimum value fifo word0 0x1b1 [15:0] x r/w stage5_min_word1 stage5 minimum value fifo word1 0x1b2 [15:0] x r/w stage5_min_word2 stage5 minimum value fifo word2 0x1b3 [15:0] x r/w stage5_min_word3 stage5 minimum value fifo word3 0x1b4 [15:0] x r/w stage5_min_avg stage5 average minimum fifo value 0x1b5 [15:0] x r/w stage5_low_thr eshold stage5 low threshold value 0x1b6 [15:0] x r/w stage5_min_temp stage5 temporary minimum value 0x1b7 [15:0] x r/w unused
AD7143 rev. 0 | page 53 of 56 table 48. stage6 results registers address data bit default type name description 0x1b8 [15:0] x r/w stage6_conv_data stage6 cdc 16-bit conversion data (copy of data in stage6_conv_data register) 0x1b9 [15:0] x r/w stage6_ff_word0 stage6 fast fifo word0 0x1ba [15:0] x r/w stage6_ff_word1 stage6 fast fifo word1 0x1bb [15:0] x r/w stage6_ff_word2 stage6 fast fifo word2 0x1bc [15:0] x r/w stage6_ff_word3 stage6 fast fifo word3 0x1bd [15:0] x r/w stage6_ff_word4 stage6 fast fifo word4 0x1be [15:0] x r/w stage6_ff_word5 stage6 fast fifo word5 0x1bf [15:0] x r/w stage6_ff_word6 stage6 fast fifo word6 0x1c0 [15:0] x r/w stage6_ff_word7 stage6 fast fifo word7 0x1c1 [15:0] x r/w stage6_sf_word0 stage6 slow fifo word0 0x1c2 [15:0] x r/w stage6_sf_word1 stage6 slow fifo word1 0x1c3 [15:0] x r/w stage6_sf_word2 stage6 slow fifo word2 0x1c4 [15:0] x r/w stage6_sf_word3 stage6 slow fifo word3 0x1c5 [15:0] x r/w stage6_sf_word4 stage6 slow fifo word4 0x1c6 [15:0] x r/w stage6_sf_word5 stage6 slow fifo word5 0x1c7 [15:0] x r/w stage6_sf_word6 stage6 slow fifo word6 0x1c8 [15:0] x r/w stage6_sf_word7 stage6 slow fifo word7 0x1c9 [15:0] x r/w stage6_sf_ambient stage6 slow fifo ambient value 0x1ca [15:0] x r/w stage6_ff_avg stage6 fast fifo average value 0x1cb [15:0] x r/w stage6_cdc_word0 stage0 cdc fifo word0 0x1cc [15:0] x r/w stage6_cdc_word1 stage6 cdc fifo word1 0x1cd [15:0] x r/w stage6_max_word0 stage6 maximum value fifo word0 0x1ce [15:0] x r/w stage6_max_word1 stage6 maximum value fifo word1 0x1cf [15:0] x r/w stage6_max_word2 stage6 maximum value fifo word2 0x1d0 [15:0] x r/w stage6_max_word3 stage6 maximum value fifo word3 0x1d1 [15:0] x r/w stage6_max_avg stage6 average maximum fifo value 0x1d2 [15:0] x r/w stage6_high_threshold stage6 high threshold value 0x1d3 [15:0] x r/w stage6_max_temp stage6 temporary maximum value 0x1d4 [15:0] x r/w stage6_min_word0 stage6 minimum value fifo word0 0x1d5 [15:0] x r/w stage6_min_word1 stage6 minimum value fifo word1 0x1d6 [15:0] x r/w stage6_min_word2 stage6 minimum value fifo word2 0x1d7 [15:0] x r/w stage6_min_word3 stage6 minimum value fifo word3 0x1d8 [15:0] x r/w stage6_min_avg stage6 average minimum fifo value 0x1d9 [15:0] x r/w stage6_low_thr eshold stage6 low threshold value 0x1da [15:0] x r/w stage6_min_temp stage6 temporary minimum value 0x1db [15:0] x r/w unused
AD7143 rev. 0 | page 54 of 56 table 49. stage7 results registers address data bit default type name description 0x1dc [15:0] x r/w stage7_conv_data stage7 cdc 16-bit conversion data (copy of data in stage7_conv_data register) 0x1dd [15:0] x r/w stage7_ff_word0 stage7 fast fifo word0 0x1de [15:0] x r/w stage7_ff_word1 stage7 fast fifo word1 0x1df [15:0] x r/w stage7_ff_word2 stage7 fast fifo word2 0x1e0 [15:0] x r/w stage7_ff_word3 stage7 fast fifo word3 0x1e1 [15:0] x r/w stage7_ff_word4 stage7 fast fifo word4 0x1e2 [15:0] x r/w stage7_ff_word5 stage7 fast fifo word5 0x1e3 [15:0] x r/w stage7_ff_word6 stage7 fast fifo word6 0x1e4 [15:0] x r/w stage7_ff_word7 stage7 fast fifo word7 0x1e5 [15:0] x r/w stage7_sf_word0 stage7 slow fifo word0 0x1e6 [15:0] x r/w stage7_sf_word1 stage7 slow fifo word1 0x1e7 [15:0] x r/w stage7_sf_word2 stage7 slow fifo word2 0x1e8 [15:0] x r/w stage7_sf_word3 stage7 slow fifo word3 0x1e9 [15:0] x r/w stage7_sf_word4 stage7 slow fifo word4 0x1ea [15:0] x r/w stage7_sf_word5 stage7 slow fifo word5 0x1eb [15:0] x r/w stage7_sf_word6 stage7 slow fifo word6 0x1ec [15:0] x r/w stage7_sf_word7 stage7 slow fifo word7 0x1ed [15:0] x r/w stage7_sf_ambient stage7 slow fifo ambient value 0x1ee [15:0] x r/w stage7_ff_avg stage7 fast fifo average value 0x1ef [15:0] x r/w stage7_cdc_word0 stage7 cdc fifo word0 0x1f0 [15:0] x r/w stage7_cdc_word1 stage7 cdc fifo word1 0x1f1 [15:0] x r/w stage7_max_word0 stage7 maximum value fifo word0 0x1f2 [15:0] x r/w stage7_max_word1 stage7 maximum value fifo word1 0x1f3 [15:0] x r/w stage7_max_word2 stage7 maximum value fifo word2 0x1f4 [15:0] x r/w stage7_max_word3 stage7 maximum value fifo word3 0x1f5 [15:0] x r/w stage7_max_avg stage7 average maximum fifo value 0x1f6 [15:0] x r/w stage7_high_threshold stage7 high threshold value 0x1f7 [15:0] x r/w stage7_max_temp stage7 temporary maximum value 0x1f8 [15:0] x r/w stage7_min_word0 stage7 minimum value fifo word0 0x1f9 [15:0] x r/w stage7_min_word1 stage7 minimum value fifo word1 0x1fa [15:0] x r/w stage7_min_word2 stage7 minimum value fifo word2 0x1fb [15:0] x r/w stage7_min_word3 stage7 minimum value fifo word3 0x1fc [15:0] x r/w stage7_min_avg stage7 average minimum fifo value 0x1fd [15:0] x r/w stage7_low_thr eshold stage7 low threshold value 0x1fe [15:0] x r/w stage7_min_temp stage7 temporary minimum value 0x1ff [15:0] x r/w unused
AD7143 rev. 0 | page 55 of 56 outline dimensions compliant to jedec standards mo-220-vggc. 1 0.65 bsc 0.60 max p i n 1 i n d i c a t o r 1.95 bcs 0.50 0.40 0.30 0.25 min 3.75 bsc sq top view 12 max 0.80 max 0.65 typ seating plane pin 1 indi c ator coplanarity 0.08 1.00 0.85 0.80 0.30 0.23 0.18 0.05 max 0.02 nom 0.20 ref 4.00 bsc sq 2.65 2.50 sq 2.35 16 5 13 8 9 12 4 exposed pa d bottom view 031006-a figure 48. 16-lead lead frame chip scale package [lfcsp_vq] 4 mm 4 mm very thin quad (cp-16-13) dimensions shown in millimeters ordering guide model temperature range serial interface desc ription package description package option AD7143acpz-1reel 1 ?40c to +85c i 2 c interface 16-lead lfcsp_vq cp-16-13 AD7143acpz-1500rl7 1 ?40c to +85c i 2 c interface 16-lead lfcsp_vq cp-16-13 eval-AD7143-1ebz 1 i 2 c interface evaluation board 1 z = pb-free part.
AD7143 rev. 0 | page 56 of 56 notes purchase of licensed i 2 c components of analog devices or one of its sublicensed associated companies conveys a license for the purchaser under the phi lips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. ?2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06472-0-1/07(0)

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